mdss: dp: set the proper parent for dp_vco_divided_clk_mux

The DP VCO divided mux clock has two parent dividers div_two
and div_four. The parent for this needs to be set based on the
link rate frequency as per the hardware programming guide and
not based on the auto PLL calculation logic. Add support to set
the correct parent for this.

Change-Id: Ia2d340a4e8790d90161c1f4a7c8273449fa3f53c
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>