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Commit ea58c08a authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ath10k: define structure for the copy engine misc regs"

parents 24ffebab 84cfceea

drivers/net/wireless/ath/ath10k/ce.c

+113 −77
Original line number Diff line number Diff line
@@ -64,7 +64,8 @@ static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);

	ar_opaque->bus_ops->write32(ar,

		ce_ctrl_addr + ar->hw_ce_regs->dst_wr_index_addr, n);

}



static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
@@ -72,8 +73,8 @@ static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					  DST_WR_INDEX_ADDRESS);

	return ar_opaque->bus_ops->read32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->dst_wr_index_addr);

}



static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
@@ -82,7 +83,8 @@ static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);

	ar_opaque->bus_ops->write32(ar,

		ce_ctrl_addr + ar->hw_ce_regs->sr_wr_index_addr, n);

}



static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
@@ -90,8 +92,8 @@ static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					  SR_WR_INDEX_ADDRESS);

	return ar_opaque->bus_ops->read32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->sr_wr_index_addr);

}



static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
@@ -99,8 +101,8 @@ static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					  CURRENT_SRRI_ADDRESS);

	return ar_opaque->bus_ops->read32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->current_srri_addr);

}



static inline void ath10k_ce_shadow_src_ring_write_index_set(struct ath10k *ar,
@@ -130,7 +132,8 @@ static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);

	ar_opaque->bus_ops->write32(ar,

		ce_ctrl_addr + ar->hw_ce_regs->sr_base_addr, addr);

}



static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
@@ -139,7 +142,8 @@ static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);

	ar_opaque->bus_ops->write32(ar,

		ce_ctrl_addr + ar->hw_ce_regs->sr_size_addr, n);

}



static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
@@ -147,12 +151,14 @@ static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar, 
					       unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;



	u32 ctrl1_addr = ar_opaque->bus_ops->read32((ar),

					   (ce_ctrl_addr) + CE_CTRL1_ADDRESS);

				(ce_ctrl_addr) + ctrl_regs->addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr &  ~CE_CTRL1_DMAX_LENGTH_MASK) |

			   CE_CTRL1_DMAX_LENGTH_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + ctrl_regs->addr,

			   (ctrl1_addr &  ~(ctrl_regs->dmax->mask)) |

			   ctrl_regs->dmax->set(n, ctrl_regs->dmax));

}



static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
@@ -160,12 +166,14 @@ static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar, 
						    unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;



	u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

						    CE_CTRL1_ADDRESS);

						    ctrl_regs->addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |

			   CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + ctrl_regs->addr,

			   (ctrl1_addr & ~(ctrl_regs->src_ring->mask)) |

			   ctrl_regs->src_ring->set(n, ctrl_regs->src_ring));

}



static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
@@ -173,12 +181,14 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, 
						     unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;



	u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

						    CE_CTRL1_ADDRESS);

						    ctrl_regs->addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |

			   CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + ctrl_regs->addr,

			   (ctrl1_addr & ~(ctrl_regs->dst_ring->mask)) |

			   ctrl_regs->dst_ring->set(n, ctrl_regs->dst_ring));

}



static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
@@ -186,8 +196,8 @@ static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					  CURRENT_DRRI_ADDRESS);

	return ar_opaque->bus_ops->read32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->current_drri_addr);

}



static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
@@ -196,7 +206,8 @@ static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);

	ar_opaque->bus_ops->write32(ar,

		ce_ctrl_addr + ar->hw_ce_regs->dr_base_addr, addr);

}



static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
@@ -205,7 +216,8 @@ static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar, 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);

	ar_opaque->bus_ops->write32(ar,

		ce_ctrl_addr + ar->hw_ce_regs->dr_size_addr, n);

}



static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
@@ -213,13 +225,12 @@ static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar, 
						   unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + srcr_wm->addr);



	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      SRC_WATERMARK_ADDRESS);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_HIGH_MASK) |

			   SRC_WATERMARK_HIGH_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + srcr_wm->addr,

			   (addr & ~(srcr_wm->wm_high->mask)) |

			   (srcr_wm->wm_high->set(n, srcr_wm->wm_high)));

}



static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
@@ -227,12 +238,12 @@ static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar, 
						  unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      SRC_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + srcr_wm->addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_LOW_MASK) |

			   SRC_WATERMARK_LOW_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + srcr_wm->addr,

			   (addr & ~(srcr_wm->wm_low->mask)) |

			   (srcr_wm->wm_low->set(n, srcr_wm->wm_low)));

}



static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
@@ -240,12 +251,12 @@ static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar, 
						    unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      DST_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + dstr_wm->addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_HIGH_MASK) |

			   DST_WATERMARK_HIGH_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + dstr_wm->addr,

			   (addr & ~(dstr_wm->wm_high->mask)) |

			   (dstr_wm->wm_high->set(n, dstr_wm->wm_high)));

}



static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
@@ -253,67 +264,82 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, 
						   unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      DST_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + dstr_wm->addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_LOW_MASK) |

			   DST_WATERMARK_LOW_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + dstr_wm->addr,

			   (addr & ~(dstr_wm->wm_low->mask)) |

			   (dstr_wm->wm_low->set(n, dstr_wm->wm_low)));

}



static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;



	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);

				ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);

	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,

			host_ie_addr | host_ie->copy_complete->mask);

}



static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;



	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);

				ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);

	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,

			host_ie_addr & ~(host_ie->copy_complete->mask));

}



static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,

						    u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;



	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);

				ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr & ~CE_WATERMARK_MASK);

	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,

			host_ie_addr & ~(wm_regs->wm_mask));

}



static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,

					       u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;



	u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + MISC_IE_ADDRESS);

			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

			   misc_ie_addr | CE_ERROR_MASK);

	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,

			misc_ie_addr | misc_regs->err_mask);

}



static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,

						u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;



	u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,

					     ce_ctrl_addr + MISC_IE_ADDRESS);

			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

			   misc_ie_addr & ~CE_ERROR_MASK);

	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,

			misc_ie_addr & ~(misc_regs->err_mask));

}



static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
@@ -321,8 +347,9 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar, 
						     unsigned int mask)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + wm_regs->addr, mask);

}



u32 shadow_sr_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr)
@@ -391,6 +418,21 @@ u32 shadow_dst_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr) 
	return addr;

}



static inline void ath10k_ce_snoc_addr_config(struct ce_desc *sdesc,

					      dma_addr_t buffer,

					      unsigned int flags)

{

	__le32 *addr = (__le32 *)&sdesc->addr;



	flags |= upper_32_bits(buffer) & CE_DESC_FLAGS_GET_MASK;

	addr[0] = __cpu_to_le32(buffer);

	addr[1] = flags;

	if (flags & CE_SEND_FLAG_GATHER)

		addr[1] |= CE_WCN3990_DESC_FLAGS_GATHER;

	else

		addr[1] &= ~CE_WCN3990_DESC_FLAGS_GATHER;

}



/*

 * Guts of ath10k_ce_send, used by both ath10k_ce_send and

 * ath10k_ce_sendlist_send.
@@ -434,17 +476,10 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, 
	if (flags & CE_SEND_FLAG_BYTE_SWAP)

		desc_flags |= CE_DESC_FLAGS_BYTE_SWAP;



	if (QCA_REV_WCN3990(ar)) {

		flags |= upper_32_bits(buffer) & CE_DESC_FLAGS_GET_MASK;

		sdesc.addr_lo = __cpu_to_le32(buffer);

		sdesc.addr_hi = flags;

		if (flags & CE_SEND_FLAG_GATHER)

			sdesc.addr_hi |= CE_WCN3990_DESC_FLAGS_GATHER;

	if (QCA_REV_WCN3990(ar))

		ath10k_ce_snoc_addr_config(&sdesc, buffer, flags);

	else

			sdesc.addr_hi &= ~CE_WCN3990_DESC_FLAGS_GATHER;

	} else {

		sdesc.addr   = __cpu_to_le32(buffer);

	}



	sdesc.nbytes = __cpu_to_le16(nbytes);

	sdesc.flags  = __cpu_to_le16(desc_flags);
@@ -866,13 +901,14 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id];

	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;

	u32 ctrl_addr = ce_state->ctrl_addr;



	spin_lock_bh(&ar_opaque->ce_lock);



	/* Clear the copy-complete interrupts that will be handled here. */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr,

					  HOST_IS_COPY_COMPLETE_MASK);

					  wm_regs->cc_mask);



	spin_unlock_bh(&ar_opaque->ce_lock);
@@ -888,7 +924,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
	 * Misc CE interrupts are not being handled, but still need

	 * to be cleared.

	 */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->wm_mask);



	spin_unlock_bh(&ar_opaque->ce_lock);

}
@@ -983,7 +1019,7 @@ void ath10k_ce_enable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id) 
	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	offset = HOST_IE_ADDRESS + ctrl_addr;

	offset = ar->hw_ce_regs->host_ie_addr + ctrl_addr;

	ar_opaque->bus_ops->write32(ar, offset, 1);

	ar_opaque->bus_ops->read32(ar, offset);

}
@@ -994,7 +1030,7 @@ void ath10k_ce_disable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id) 
	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);



	offset = HOST_IE_ADDRESS + ctrl_addr;

	offset = ar->hw_ce_regs->host_ie_addr + ctrl_addr;

	ar_opaque->bus_ops->write32(ar, offset, 0);

	ar_opaque->bus_ops->read32(ar, offset);

}

drivers/net/wireless/ath/ath10k/ce.h

+1 −324

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/ath/ath10k/core.c

+6 −0
Original line number Diff line number Diff line
@@ -2324,28 +2324,34 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 
	case ATH10K_HW_QCA988X:

	case ATH10K_HW_QCA9887:

		ar->regs = &qca988x_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca988x_values;

		break;

	case ATH10K_HW_QCA6174:

	case ATH10K_HW_QCA9377:

		ar->regs = &qca6174_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca6174_values;

		break;

	case ATH10K_HW_QCA99X0:

	case ATH10K_HW_QCA9984:

		ar->regs = &qca99x0_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca99x0_values;

		break;

	case ATH10K_HW_QCA9888:

		ar->regs = &qca99x0_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca9888_values;

		break;

	case ATH10K_HW_QCA4019:

		ar->regs = &qca4019_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca4019_values;

		break;

	case ATH10K_HW_WCN3990:

		ar->regs = &wcn3990_regs;

		ar->hw_ce_regs = &wcn3990_ce_regs;

		ar->hw_values = &wcn3990_values;

		/* WCN3990 chip set is non bmi based */

		ar->is_bmi = false;

drivers/net/wireless/ath/ath10k/core.h

+1 −0
Original line number Diff line number Diff line
@@ -740,6 +740,7 @@ struct ath10k { 
	struct completion target_suspend;



	const struct ath10k_hw_regs *regs;

	const struct ath10k_hw_ce_regs *hw_ce_regs;

	const struct ath10k_hw_values *hw_values;

	struct ath10k_shadow_reg_value *shadow_reg_value;

	struct ath10k_shadow_reg_address *shadow_reg_address;

drivers/net/wireless/ath/ath10k/htt.h

+2 −2
Original line number Diff line number Diff line
@@ -541,6 +541,7 @@ struct htt_rx_indication_hdr { 
#define HTT_RX_INDICATION_INFO2_SERVICE_LSB     24



#define HTT_WCN3990_PADDR_MASK 0x1F

#define HTT_WCN3990_ARCH_PADDR_MASK 0x1FFFFFFFFF



enum htt_rx_legacy_rate {

	HTT_RX_OFDM_48 = 0,
@@ -865,8 +866,7 @@ struct htt_rx_offload_ind { 


struct htt_rx_in_ord_msdu_desc {

#ifdef CONFIG_ATH10K_SNOC

	__le32 msdu_paddr_lo;

	__le32 msdu_paddr_hi;

	__le64 msdu_paddr;

#else

	__le32 msdu_paddr;

#endif