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Commit 84cfceea authored by Sarada Prasanna Garnayak's avatar Sarada Prasanna Garnayak Committed by Gerrit - the friendly Code Review server
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ath10k: define structure for the copy engine misc regs 



Define structures for the copy engine misc registers
copy engine CMD halt, watermark source, watermark
destination, host IE ring.

This adds support to avoid the conditional compilation,
code optimization and dynamic configuration of the copy
engine register map for respective hardware bus interface.

Change-Id: I42b9c0ad0927b492e3b4f040ae7163456b161735
Signed-off-by: default avatarSarada Prasanna Garnayak <sgarna@codeaurora.org>
parent ff6155fa

drivers/net/wireless/ath/ath10k/ce.c

+40 −29
Original line number Diff line number Diff line
@@ -225,13 +225,12 @@ static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar, 
						   unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + srcr_wm->addr);



	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      SRC_WATERMARK_ADDRESS);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_HIGH_MASK) |

			   SRC_WATERMARK_HIGH_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + srcr_wm->addr,

			   (addr & ~(srcr_wm->wm_high->mask)) |

			   (srcr_wm->wm_high->set(n, srcr_wm->wm_high)));

}



static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
@@ -239,12 +238,12 @@ static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar, 
						  unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      SRC_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + srcr_wm->addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_LOW_MASK) |

			   SRC_WATERMARK_LOW_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + srcr_wm->addr,

			   (addr & ~(srcr_wm->wm_low->mask)) |

			   (srcr_wm->wm_low->set(n, srcr_wm->wm_low)));

}



static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
@@ -252,12 +251,12 @@ static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar, 
						    unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      DST_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + dstr_wm->addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_HIGH_MASK) |

			   DST_WATERMARK_HIGH_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + dstr_wm->addr,

			   (addr & ~(dstr_wm->wm_high->mask)) |

			   (dstr_wm->wm_high->set(n, dstr_wm->wm_high)));

}



static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
@@ -265,72 +264,82 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, 
						   unsigned int n)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +

					      DST_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;

	u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + dstr_wm->addr);



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_LOW_MASK) |

			   DST_WATERMARK_LOW_SET(n));

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + dstr_wm->addr,

			   (addr & ~(dstr_wm->wm_low->mask)) |

			   (dstr_wm->wm_low->set(n, dstr_wm->wm_low)));

}



static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;



	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,

				ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);



	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,

			host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);

			host_ie_addr | host_ie->copy_complete->mask);

}



static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;



	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,

				ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);



	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,

			host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);

			host_ie_addr & ~(host_ie->copy_complete->mask));

}



static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,

						    u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;



	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,

				ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);



	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,

			host_ie_addr & ~CE_WATERMARK_MASK);

			host_ie_addr & ~(wm_regs->wm_mask));

}



static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,

					       u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;



	u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);



	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,

			misc_ie_addr | CE_ERROR_MASK);

			misc_ie_addr | misc_regs->err_mask);

}



static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,

						u32 ce_ctrl_addr)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;



	u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);



	ar_opaque->bus_ops->write32(ar,

			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,

			misc_ie_addr & ~CE_ERROR_MASK);

			misc_ie_addr & ~(misc_regs->err_mask));

}



static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
@@ -338,8 +347,9 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar, 
						     unsigned int mask)

{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;



	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);

	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + wm_regs->addr, mask);

}



u32 shadow_sr_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr)
@@ -891,13 +901,14 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
{

	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id];

	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;

	u32 ctrl_addr = ce_state->ctrl_addr;



	spin_lock_bh(&ar_opaque->ce_lock);



	/* Clear the copy-complete interrupts that will be handled here. */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr,

					  HOST_IS_COPY_COMPLETE_MASK);

					  wm_regs->cc_mask);



	spin_unlock_bh(&ar_opaque->ce_lock);
@@ -913,7 +924,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
	 * Misc CE interrupts are not being handled, but still need

	 * to be cleared.

	 */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->wm_mask);



	spin_unlock_bh(&ar_opaque->ce_lock);

}

drivers/net/wireless/ath/ath10k/ce.h

+0 −203
Original line number Diff line number Diff line
@@ -356,197 +356,6 @@ struct ce_attr { 
	void (*recv_cb)(struct ath10k_ce_pipe *);

};



#ifndef CONFIG_ATH10K_SNOC

#define CE_CMD_HALT_STATUS_MSB			3

#define CE_CMD_HALT_STATUS_LSB			3

#define CE_CMD_HALT_STATUS_MASK			0x00000008

#define CE_CMD_HALT_STATUS_GET(x) \

	(((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB)

#define CE_CMD_HALT_STATUS_SET(x) \

	(((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK)

#define CE_CMD_HALT_STATUS_RESET		0

#define CE_CMD_HALT_MSB				0

#define CE_CMD_HALT_MASK			0x00000001



#define HOST_IE_COPY_COMPLETE_MSB		0

#define HOST_IE_COPY_COMPLETE_LSB		0

#define HOST_IE_COPY_COMPLETE_MASK		0x00000001

#define HOST_IE_COPY_COMPLETE_GET(x) \

	(((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB)

#define HOST_IE_COPY_COMPLETE_SET(x) \

	(((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)

#define HOST_IE_COPY_COMPLETE_RESET		0



#define HOST_IS_DST_RING_LOW_WATERMARK_MASK	0x00000010

#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK	0x00000008

#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK	0x00000004

#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK	0x00000002

#define HOST_IS_COPY_COMPLETE_MASK		0x00000001

#define HOST_IS_ADDRESS				0x0030



#define MISC_IS_AXI_ERR_MASK			0x00000400



#define MISC_IS_DST_ADDR_ERR_MASK		0x00000200

#define MISC_IS_SRC_LEN_ERR_MASK		0x00000100

#define MISC_IS_DST_MAX_LEN_VIO_MASK		0x00000080

#define MISC_IS_DST_RING_OVERFLOW_MASK		0x00000040

#define MISC_IS_SRC_RING_OVERFLOW_MASK		0x00000020



#define MISC_IS_ADDRESS				0x0038



#define SRC_WATERMARK_LOW_MSB			31

#define SRC_WATERMARK_LOW_LSB			16

#define SRC_WATERMARK_LOW_MASK			0xffff0000

#define SRC_WATERMARK_LOW_GET(x) \

	(((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)

#define SRC_WATERMARK_LOW_SET(x) \

	(((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)

#define SRC_WATERMARK_LOW_RESET			0

#define SRC_WATERMARK_HIGH_MSB			15

#define SRC_WATERMARK_HIGH_LSB			0

#define SRC_WATERMARK_HIGH_MASK			0x0000ffff

#define SRC_WATERMARK_HIGH_GET(x) \

	(((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)

#define SRC_WATERMARK_HIGH_SET(x) \

	(((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)

#define SRC_WATERMARK_HIGH_RESET		0

#define SRC_WATERMARK_ADDRESS			0x004c



#define DST_WATERMARK_LOW_LSB			16

#define DST_WATERMARK_LOW_MASK			0xffff0000

#define DST_WATERMARK_LOW_SET(x) \

	(((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)

#define DST_WATERMARK_LOW_RESET			0

#define DST_WATERMARK_HIGH_MSB			15

#define DST_WATERMARK_HIGH_LSB			0

#define DST_WATERMARK_HIGH_MASK			0x0000ffff

#define DST_WATERMARK_HIGH_GET(x) \

	(((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)

#define DST_WATERMARK_HIGH_SET(x) \

	(((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)

#define DST_WATERMARK_HIGH_RESET		0

#define DST_WATERMARK_ADDRESS			0x0050



#else

#define WCN3990_CE0_SR_BA_LOW		(0x00240000)

#define WCN3990_CE1_SR_BA_LOW		(0x00241000)

#define WCN3990_CE2_SR_BA_LOW		(0x00242000)

#define WCN3990_CE3_SR_BA_LOW		(0x00243000)

#define WCN3990_CE4_SR_BA_LOW		(0x00244000)

#define WCN3990_CE5_SR_BA_LOW		(0x00245000)

#define WCN3990_CE6_SR_BA_LOW		(0x00246000)

#define WCN3990_CE7_SR_BA_LOW		(0x00247000)

#define WCN3990_CE8_SR_BA_LOW		(0x00248000)

#define WCN3990_CE9_SR_BA_LOW		(0x00249000)

#define WCN3990_CE10_SR_BA_LOW		(0x0024A000)

#define WCN3990_CE11_SR_BA_LOW		(0x0024B000)

#define WCN3990_CE0_DR_BA_LOW		(0x0024000C)

#define WNC3990_CE0_DR_SIZE		(0x00240014)

#define WCN3990_CE0_CE_CTRL1		(0x00240018)

#define WCN3990_CE0_HOST_IE		(0x0024002C)

#define WCN3990_CE0_HOST_IS		(0x00240030)

#define WCN3990_CE0_MISC_IE		(0x00240034)

#define WCN3990_CE0_MISC_IS		(0x00240038)

#define WCN3990_CE0_SRC_WR_INDEX	(0x0024003C)

#define WCN3990_CE0_CURRENT_SRRI	(0x00240044)

#define WCN3990_CE0_CURRENT_DRRI	(0x00240048)

#define WCN3990_CE0_SRC_WATERMARK	(0x0024004C)

#define WCN3990_CE0_DST_WATERMARK	(0x00240050)

#define WCN3990_CE0_SR_SIZE		(0x00240008)

#define HOST_IE_COPY_COMPLETE_MASK	(0x00000001)

#define WCN3990_CE_WRAPPER_HOST_INTERRUPT_SUMMARY	0x0024C000

#define WCN3990_CE_WRAPPER_INDEX_BASE_LOW		0x0024C004

#define WCN3990_CE_WRAPPER_INDEX_BASE_HIGH		0x0024C008

#define CE_CTRL1_IDX_UPD_EN				0x00080000



#define WCN3990_CE_WRAPPER_BASE_ADDRESS \

			WCN3990_CE_WRAPPER_HOST_INTERRUPT_SUMMARY

#define WCN3990_CE0_BASE_ADDRESS \

			WCN3990_CE0_SR_BA_LOW

#define WCN3990_CE1_BASE_ADDRESS \

			WCN3990_CE1_SR_BA_LOW

#define WCN3990_CE2_BASE_ADDRESS \

			WCN3990_CE2_SR_BA_LOW

#define WCN3990_CE3_BASE_ADDRESS \

			WCN3990_CE3_SR_BA_LOW

#define WCN3990_CE4_BASE_ADDRESS \

			WCN3990_CE4_SR_BA_LOW

#define WCN3990_CE5_BASE_ADDRESS \

			WCN3990_CE5_SR_BA_LOW

#define WCN3990_CE6_BASE_ADDRESS \

			WCN3990_CE6_SR_BA_LOW

#define WCN3990_CE7_BASE_ADDRESS \

			WCN3990_CE7_SR_BA_LOW

#define WCN3990_CE8_BASE_ADDRESS \

			WCN3990_CE8_SR_BA_LOW

#define WCN3990_CE9_BASE_ADDRESS \

			WCN3990_CE9_SR_BA_LOW

#define WCN3990_CE10_BASE_ADDRESS \

			WCN3990_CE10_SR_BA_LOW

#define WCN3990_CE11_BASE_ADDRESS \

			WCN3990_CE11_SR_BA_LOW



#define HOST_IS_DST_RING_LOW_WATERMARK_MASK	0x00000010

#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK	0x00000008

#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK	0x00000004

#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK	0x00000002

#define HOST_IS_COPY_COMPLETE_MASK		0x00000001

#define HOST_IS_ADDRESS		(WCN3990_CE0_HOST_IS \

				- WCN3990_CE0_BASE_ADDRESS)



#define MISC_IS_AXI_ERR_MASK			0x00000100

#define MISC_IS_DST_ADDR_ERR_MASK		0x00000200

#define MISC_IS_SRC_LEN_ERR_MASK		0x00000100

#define MISC_IS_DST_MAX_LEN_VIO_MASK		0x00000080

#define MISC_IS_DST_RING_OVERFLOW_MASK		0x00000040

#define MISC_IS_SRC_RING_OVERFLOW_MASK		0x00000020

#define MISC_IS_ADDRESS		(WCN3990_CE0_MISC_IS \

				- WCN3990_CE0_BASE_ADDRESS)



#define SRC_WATERMARK_LOW_MSB			0

#define SRC_WATERMARK_LOW_LSB			16



#define SRC_WATERMARK_LOW_MASK			0xffff0000

#define SRC_WATERMARK_LOW_GET(x) \

	(((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)

#define SRC_WATERMARK_LOW_SET(x) \

	(((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)



#define SRC_WATERMARK_LOW_RESET			0

#define SRC_WATERMARK_HIGH_MSB			15

#define SRC_WATERMARK_HIGH_LSB			0

#define SRC_WATERMARK_HIGH_MASK			0x0000ffff

#define SRC_WATERMARK_HIGH_GET(x) \

	(((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)

#define SRC_WATERMARK_HIGH_SET(x) \

	(((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)



#define SRC_WATERMARK_HIGH_RESET		0

#define SRC_WATERMARK_ADDRESS	(WCN3990_CE0_SRC_WATERMARK\

					- WCN3990_CE0_BASE_ADDRESS)



#define DST_WATERMARK_LOW_LSB			16

#define DST_WATERMARK_LOW_MASK			0xffff0000

#define DST_WATERMARK_LOW_SET(x) \

	(((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)

#define DST_WATERMARK_LOW_RESET			0

#define DST_WATERMARK_HIGH_MSB			15

#define DST_WATERMARK_HIGH_LSB			0

#define DST_WATERMARK_HIGH_MASK			0x0000ffff

#define DST_WATERMARK_HIGH_GET(x) \

	(((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)

#define DST_WATERMARK_HIGH_SET(x) \

	(((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)

#define DST_WATERMARK_HIGH_RESET		0

#define DST_WATERMARK_ADDRESS	(WCN3990_CE0_DST_WATERMARK \

						- WCN3990_CE0_BASE_ADDRESS)



#define BITS0_TO_31(val) ((uint32_t)((uint64_t)(val)\

				     & (uint64_t)(0xFFFFFFFF)))

#define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(val)\

				     & (uint64_t)(0xF00000000)) >> 32))

#endif



#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \

		- CE0_BASE_ADDRESS) / (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
@@ -555,18 +364,6 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) 
	return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;

}



#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK  | \

			   HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \

			   HOST_IS_DST_RING_LOW_WATERMARK_MASK  | \

			   HOST_IS_DST_RING_HIGH_WATERMARK_MASK)



#define CE_ERROR_MASK	(MISC_IS_AXI_ERR_MASK           | \

			 MISC_IS_DST_ADDR_ERR_MASK      | \

			 MISC_IS_SRC_LEN_ERR_MASK       | \

			 MISC_IS_DST_MAX_LEN_VIO_MASK   | \

			 MISC_IS_DST_RING_OVERFLOW_MASK | \

			 MISC_IS_SRC_RING_OVERFLOW_MASK)



#define CE_SRC_RING_TO_DESC(baddr, idx) \

	(&(((struct ce_desc *)baddr)[idx]))

drivers/net/wireless/ath/ath10k/hw.c

+181 −0
Original line number Diff line number Diff line
@@ -209,6 +209,81 @@ struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = { 
	.dmax		= &wcn3990_dmax,

};



struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = {

	.mask	= 0x00000001,

};



struct ath10k_hw_ce_host_ie wcn3990_host_ie = {

	.copy_complete	= &wcn3990_host_ie_cc,

};



struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {

	.dstr_lmask	= 0x00000010,

	.dstr_hmask	= 0x00000008,

	.srcr_lmask	= 0x00000004,

	.srcr_hmask	= 0x00000002,

	.cc_mask	= 0x00000001,

	.wm_mask	= 0x0000001E,

	.addr		= 0x00000030,

};



struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {

	.axi_err	= 0x00000100,

	.dstr_add_err	= 0x00000200,

	.srcr_len_err	= 0x00000100,

	.dstr_mlen_vio	= 0x00000080,

	.dstr_overflow	= 0x00000040,

	.srcr_overflow	= 0x00000020,

	.err_mask	= 0x000003E0,

	.addr		= 0x00000038,

};



struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = {

	.msb	= 0x00000000,

	.lsb	= 0x00000010,

	.mask	= 0xffff0000,

	.set	= &ath10k_set_ring_byte,

	.get	= &ath10k_get_ring_byte,

};



struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = {

	.msb	= 0x0000000f,

	.lsb	= 0x00000000,

	.mask	= 0x0000ffff,

	.set	= &ath10k_set_ring_byte,

	.get	= &ath10k_get_ring_byte,

};



struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {

	.addr		= 0x0000004c,

	.low_rst	= 0x00000000,

	.high_rst	= 0x00000000,

	.wm_low		= &wcn3990_src_wm_low,

	.wm_high	= &wcn3990_src_wm_high,

};



struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = {

	.lsb	= 0x00000010,

	.mask	= 0xffff0000,

	.set	= &ath10k_set_ring_byte,

};



struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = {

	.msb	= 0x0000000f,

	.lsb	= 0x00000000,

	.mask	= 0x0000ffff,

	.set	= &ath10k_set_ring_byte,

	.get	= &ath10k_get_ring_byte,

};



struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {

	.addr		= 0x00000050,

	.low_rst	= 0x00000000,

	.high_rst	= 0x00000000,

	.wm_low		= &wcn3990_dst_wm_low,

	.wm_high	= &wcn3990_dst_wm_high,

};



struct ath10k_hw_ce_regs wcn3990_ce_regs = {

	.sr_base_addr		= 0x00000000,

	.sr_size_addr		= 0x00000008,
@@ -225,6 +300,11 @@ struct ath10k_hw_ce_regs wcn3990_ce_regs = { 
	.ce_rri_high		= 0x0024C008,

	.host_ie_addr		= 0x0000002c,

	.ctrl1_regs		= &wcn3990_ctrl1,

	.host_ie		= &wcn3990_host_ie,

	.wm_regs		= &wcn3990_wm_reg,

	.misc_regs		= &wcn3990_misc_reg,

	.wm_srcr		= &wcn3990_wm_src_ring,

	.wm_dstr		= &wcn3990_wm_dst_ring,

};



struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
@@ -263,6 +343,101 @@ struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = { 
	.dmax		= &qcax_dmax,

};



struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = {

	.msb	= 0x00000003,

	.lsb	= 0x00000003,

	.mask	= 0x00000008,

	.set	= &ath10k_set_ring_byte,

	.get	= &ath10k_get_ring_byte,

};



struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = {

	.msb		= 0x00000000,

	.mask		= 0x00000001,

	.status_reset	= 0x00000000,

	.status		= &qcax_cmd_halt_status,

};



struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = {

	.msb	= 0x00000000,

	.lsb	= 0x00000000,

	.mask	= 0x00000001,

	.set	= &ath10k_set_ring_byte,

	.get	= &ath10k_get_ring_byte,

};



struct ath10k_hw_ce_host_ie qcax_host_ie = {

	.copy_complete_reset	= 0x00000000,

	.copy_complete		= &qcax_host_ie_cc,

};



struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {

	.dstr_lmask	= 0x00000010,

	.dstr_hmask	= 0x00000008,

	.srcr_lmask	= 0x00000004,

	.srcr_hmask	= 0x00000002,

	.cc_mask	= 0x00000001,

	.wm_mask	= 0x0000001E,

	.addr		= 0x00000030,

};



struct ath10k_hw_ce_misc_regs qcax_misc_reg = {

	.axi_err	= 0x00000400,

	.dstr_add_err	= 0x00000200,

	.srcr_len_err	= 0x00000100,

	.dstr_mlen_vio	= 0x00000080,

	.dstr_overflow	= 0x00000040,

	.srcr_overflow	= 0x00000020,

	.err_mask	= 0x000007E0,

	.addr		= 0x00000038,

};



struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = {

	.msb    = 0x0000001f,

	.lsb	= 0x00000010,

	.mask	= 0xffff0000,

	.set	= &ath10k_set_ring_byte,

	.get	= &ath10k_get_ring_byte,

};



struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = {

	.msb	= 0x0000000f,

	.lsb	= 0x00000000,

	.mask	= 0x0000ffff,

	.set	= &ath10k_set_ring_byte,

	.get	= &ath10k_get_ring_byte,

};



struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {

	.addr		= 0x0000004c,

	.low_rst	= 0x00000000,

	.high_rst	= 0x00000000,

	.wm_low		= &qcax_src_wm_low,

	.wm_high        = &qcax_src_wm_high,

};



struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = {

	.lsb	= 0x00000010,

	.mask	= 0xffff0000,

	.set	= &ath10k_set_ring_byte,

};



struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = {

	.msb	= 0x0000000f,

	.lsb	= 0x00000000,

	.mask	= 0x0000ffff,

	.set	= &ath10k_set_ring_byte,

	.get	= &ath10k_get_ring_byte,

};



struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = {

	.addr		= 0x00000050,

	.low_rst	= 0x00000000,

	.high_rst	= 0x00000000,

	.wm_low		= &qcax_dst_wm_low,

	.wm_high	= &qcax_dst_wm_high,

};



struct ath10k_hw_ce_regs qcax_ce_regs = {

	.sr_base_addr		= 0x00000000,

	.sr_size_addr		= 0x00000004,
@@ -276,6 +451,12 @@ struct ath10k_hw_ce_regs qcax_ce_regs = { 
	.current_drri_addr	= 0x00000048,

	.host_ie_addr		= 0x0000002c,

	.ctrl1_regs		= &qcax_ctrl1,

	.cmd_halt		= &qcax_cmd_halt,

	.host_ie		= &qcax_host_ie,

	.wm_regs		= &qcax_wm_reg,

	.misc_regs		= &qcax_misc_reg,

	.wm_srcr		= &qcax_wm_src_ring,

	.wm_dstr                = &qcax_wm_dst_ring,

};



const struct ath10k_hw_values qca988x_values = {

drivers/net/wireless/ath/ath10k/hw.h

+47 −0
Original line number Diff line number Diff line
@@ -291,6 +291,47 @@ struct ath10k_hw_ce_ctrl1 { 
	struct ath10k_hw_ce_regs_addr_map *dmax;

};



struct ath10k_hw_ce_cmd_halt {

	u32 status_reset;

	u32 msb;

	u32 mask;

	struct ath10k_hw_ce_regs_addr_map *status;

};



struct ath10k_hw_ce_host_ie {

	u32 copy_complete_reset;

	struct ath10k_hw_ce_regs_addr_map *copy_complete;

};



struct ath10k_hw_ce_host_wm_regs {

	u32 dstr_lmask;

	u32 dstr_hmask;

	u32 srcr_lmask;

	u32 srcr_hmask;

	u32 cc_mask;

	u32 wm_mask;

	u32 addr;

};



struct ath10k_hw_ce_misc_regs {

	u32 axi_err;

	u32 dstr_add_err;

	u32 srcr_len_err;

	u32 dstr_mlen_vio;

	u32 dstr_overflow;

	u32 srcr_overflow;

	u32 err_mask;

	u32 addr;

};



struct ath10k_hw_ce_dst_src_wm_regs {

	u32 addr;

	u32 low_rst;

	u32 high_rst;

	struct ath10k_hw_ce_regs_addr_map *wm_low;

	struct ath10k_hw_ce_regs_addr_map *wm_high;

};



struct ath10k_hw_ce_regs {

	u32 sr_base_addr;

	u32 sr_size_addr;
@@ -307,7 +348,13 @@ struct ath10k_hw_ce_regs { 
	u32 ce_rri_low;

	u32 ce_rri_high;

	u32 host_ie_addr;

	struct ath10k_hw_ce_host_wm_regs *wm_regs;

	struct ath10k_hw_ce_misc_regs *misc_regs;

	struct ath10k_hw_ce_ctrl1 *ctrl1_regs;

	struct ath10k_hw_ce_cmd_halt *cmd_halt;

	struct ath10k_hw_ce_host_ie *host_ie;

	struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;

	struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr;

};



extern struct ath10k_hw_ce_regs wcn3990_ce_regs;