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Commit e9719c41 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add support for USB device for msmfalcon and msmtriton"

parents b2c7e8b3 291a7d13

arch/arm/boot/dts/qcom/msmfalcon-common.dtsi

0 → 100644
+196 −0
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	usb3: ssusb@a800000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x0a800000 0xfc100>,

			<0x0c016000 0x400>;

		reg-names = "core_base",

		"ahb2phy_base";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		interrupts = <0 347 0>, <0 243 0>, <0 180 0>;

		interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";



		USB3_GDSC-supply = <&gdsc_usb30>;



		qcom,usb-dbm = <&dbm_1p5>;

		qcom,msm-bus,name = "usb3";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<61 512 0 0>,

				<61 512 240000 800000>;



		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;



		clocks = <&clock_gcc GCC_USB30_MASTER_CLK>,

			<&clock_gcc GCC_CFG_NOC_USB3_AXI_CLK>,

			<&clock_gcc GCC_AGGRE2_USB3_AXI_CLK>,

			<&clock_gcc GCC_USB30_MOCK_UTMI_CLK>,

			<&clock_gcc GCC_USB30_SLEEP_CLK>,

			<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

			<&clock_rpmcc CXO_DWC3_CLK>;



		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

				"utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";



		resets = <&clock_gcc GCC_USB_30_BCR>;

		reset-names = "core_reset";



		dwc3@a800000 {

			compatible = "snps,dwc3";

			reg = <0x0a800000 0xc8d0>;

			interrupt-parent = <&intc>;

			interrupts = <0 131 0>;

			usb-phy = <&qusb_phy0>, <&ssphy>;

			tx-fifo-resize;

			snps,usb3-u1u2-disable;

			snps,nominal-elastic-buffer;

			snps,is-utmi-l1-suspend;

			snps,hird-threshold = /bits/ 8 <0x0>;

		};



		qcom,usbbam@a904000 {

			compatible = "qcom,usb-bam-msm";

			reg = <0x0a904000 0x17000>;

			interrupt-parent = <&intc>;

			interrupts = <0 132 0>;



			qcom,bam-type = <0>;

			qcom,usb-bam-fifo-baseaddr = <0x066bb000>;

			qcom,usb-bam-num-pipes = <8>;

			qcom,ignore-core-reset-ack;

			qcom,disable-clk-gating;

			qcom,usb-bam-override-threshold = <0x4001>;

			qcom,usb-bam-max-mbps-highspeed = <400>;

			qcom,usb-bam-max-mbps-superspeed = <3600>;

			qcom,reset-bam-on-connect;



			qcom,pipe0 {

				label = "ssusb-ipa-out-0";

				qcom,usb-bam-mem-type = <1>;

				qcom,dir = <0>;

				qcom,pipe-num = <0>;

				qcom,peer-bam = <1>;

				qcom,src-bam-pipe-index = <1>;

				qcom,data-fifo-size = <0x8000>;

				qcom,descriptor-fifo-size = <0x2000>;

			};

			qcom,pipe1 {

				label = "ssusb-ipa-in-0";

				qcom,usb-bam-mem-type = <1>;

				qcom,dir = <1>;

				qcom,pipe-num = <0>;

				qcom,peer-bam = <1>;

				qcom,dst-bam-pipe-index = <0>;

				qcom,data-fifo-size = <0x8000>;

				qcom,descriptor-fifo-size = <0x2000>;

			};

			qcom,pipe2 {

				label = "ssusb-qdss-in-0";

				qcom,usb-bam-mem-type = <2>;

				qcom,dir = <1>;

				qcom,pipe-num = <0>;

				qcom,peer-bam = <0>;

				qcom,peer-bam-physical-address = <0x06064000>;

				qcom,src-bam-pipe-index = <0>;

				qcom,dst-bam-pipe-index = <2>;

				qcom,data-fifo-offset = <0x0>;

				qcom,data-fifo-size = <0x1800>;

				qcom,descriptor-fifo-offset = <0x1800>;

				qcom,descriptor-fifo-size = <0x800>;

			};

			qcom,pipe3 {

				label = "ssusb-dpl-ipa-in-1";

				qcom,usb-bam-mem-type = <1>;

				qcom,dir = <1>;

				qcom,pipe-num = <1>;

				qcom,peer-bam = <1>;

				qcom,dst-bam-pipe-index = <2>;

				qcom,data-fifo-size = <0x8000>;

				qcom,descriptor-fifo-size = <0x2000>;

			};

		};

	};



	qusb_phy0: qusb@c012000 {

		compatible = "qcom,qusb2phy";

		reg = <0x0c012000 0x180>,

			<0x00188018 0x4>;

		reg-names = "qusb_phy_base",

			"ref_clk_addr";

		vdd-supply = <&pm2falcon_l1>;

		vdda18-supply = <&pmfalcon_l10>;

		vdda33-supply = <&pm2falcon_l7>;

		qcom,vdd-voltage-level = <0 925000 925000>;

		qcom,tune2-efuse-bit-pos = <21>;

		qcom,tune2-efuse-num-bits = <4>;

		qcom,enable-dpdm-pulsing;

		qcom,qusb-phy-init-seq = <0xf8 0x80

					0xb3 0x84

					0x83 0x88

					0xc0 0x8c

					0x30 0x08

					0x79 0x0c

					0x21 0x10

					0x14 0x9c

					0x9f 0x1c

					0x00 0x18>;

		phy_type= "utmi";



		clocks = <&clock_rpmcc RPM_LN_BB_CLK1>,

			<&clock_gcc GCC_RX0_USB2_CLKREF_CLK>,

			<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;



		clock-names =  "ref_clk_src", "ref_clk", "cfg_ahb_clk";



		resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;

		reset-names = "phy_reset";

	};



	ssphy: ssphy@c010000 {

		compatible = "qcom,usb-ssphy-qmp-v2";

		reg = <0xc010000 0x7a8>,

			<0x01fcb244 0x4>,

			<0x01fcb248 0x4>;

		reg-names = "qmp_phy_base",

			"vls_clamp_reg",

			"tcsr_usb3_dp_phymode";

		vdd-supply = <&pm2falcon_l1>;

		core-supply = <&pmfalcon_l10>;

		qcom,vdd-voltage-level = <0 925000 925000>;

		qcom,vbus-valid-override;



		clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>,

			<&clock_gcc GCC_USB3_PHY_PIPE_CLK>,

			<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

			<&clock_rpmcc RPM_LN_BB_CLK1>,

			<&clock_gcc GCC_USB3_CLKREF_CLK>;



		clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",

				"ref_clk_src", "ref_clk";



		resets = <&clock_gcc GCC_USB3_PHY_BCR>,

			<&clock_gcc GCC_USB3PHY_PHY_BCR>;

		reset-names = "phy_reset", "phy_phy_reset";

	};



	dbm_1p5: dbm@a8f8000 {

		compatible = "qcom,usb-dbm-1p5";

		reg = <0xa8f8000 0x300>;

		qcom,reset-ep-after-lpm-resume;

	};

};

arch/arm/boot/dts/qcom/msmfalcon-rumi.dts

+32 −0
Original line number Diff line number Diff line
@@ -26,6 +26,38 @@ 
	};

};



&usb3 {

	/delete-property/ USB3_GDSC-supply;

	dwc3@a800000 {

		maximum-speed = "high-speed";

	};

};



&ssphy {

	compatible =  "usb-nop-xceiv";

};



&qusb_phy0 {

	reg = <0x0a928000 0x8000>,

		<0x0a8f8800 0x400>,

		<0x0a920000 0x100>;

		reg-names = "qusb_phy_base",

			"qscratch_base",

			"emu_phy_base";

		qcom,emulation;

		qcom,qusb-phy-init-seq = <0x19 0x1404

					0x20 0x1414

					0x79 0x1410

					0x00 0x1418

					0x99 0x1404

					0x04 0x1408

					0xd9 0x1404>;

		qcom,emu-dcm-reset-seq = <0x100000 0x20

					0x0 0x20

					0x1a0 0x20

					0x5 0x14>;

};



&uartblsp1dm1 {

	status = "ok";

	pinctrl-names = "default";

arch/arm/boot/dts/qcom/msmfalcon-sim.dts

+16 −0
Original line number Diff line number Diff line
@@ -26,6 +26,22 @@ 
	};

};



&usb3 {

	reg = <0xa800000 0xfc000>;

	reg-names = "core_base";

	dwc3@a800000 {

		maximum-speed = "high-speed";

	};

};



&ssphy {

	compatible =  "usb-nop-xceiv";

};



&qusb_phy0 {

	compatible =  "usb-nop-xceiv";

};



&uartblsp1dm1 {

	status = "ok";

	pinctrl-names = "default";

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1000,4 +1000,5 @@ 
#include "msm-pm2falcon.dtsi"

#include "msm-arm-smmu-falcon.dtsi"

#include "msm-arm-smmu-impl-defs-falcon.dtsi"

#include "msmfalcon-common.dtsi"

#include "msmfalcon-blsp.dtsi"

arch/arm/boot/dts/qcom/msmtriton-rumi.dts

+31 −0
Original line number Diff line number Diff line
@@ -22,6 +22,37 @@ 
	qcom,board-id = <15 0>;

};



&usb3 {

	dwc3@a800000 {

		maximum-speed = "high-speed";

	};

};



&ssphy {

	compatible =  "usb-nop-xceiv";

};



&qusb_phy0 {

	reg = <0x0a928000 0x8000>,

		<0x0a8f8800 0x400>,

		<0x0a920000 0x100>;

	reg-names = "qusb_phy_base",

		"qscratch_base",

		"emu_phy_base";

	qcom,emulation;

	qcom,qusb-phy-init-seq = <0x19 0x1404

				0x20 0x1414

				0x79 0x1410

				0x00 0x1418

				0x99 0x1404

				0x04 0x1408

				0xd9 0x1404>;

	qcom,emu-dcm-reset-seq = <0x100000 0x20

				0x0 0x20

				0x1a0 0x20

				0x5 0x14>;

};



&uartblsp1dm1 {

	status = "ok";

	pinctrl-names = "default";