Loading arch/arm64/include/asm/cputype.h +2 −0 Original line number Diff line number Diff line Loading @@ -99,6 +99,8 @@ #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_KRYO2XX_SILVER \ MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER) #define MIDR_KRYO2XX_GOLD \ MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD) #ifndef __ASSEMBLY__ Loading arch/arm64/kernel/cpu_errata.c +5 −0 Original line number Diff line number Diff line Loading @@ -225,6 +225,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), .enable = enable_psci_bp_hardening, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_KRYO2XX_GOLD), .enable = enable_psci_bp_hardening, }, #endif { } Loading Loading
arch/arm64/include/asm/cputype.h +2 −0 Original line number Diff line number Diff line Loading @@ -99,6 +99,8 @@ #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_KRYO2XX_SILVER \ MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER) #define MIDR_KRYO2XX_GOLD \ MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD) #ifndef __ASSEMBLY__ Loading
arch/arm64/kernel/cpu_errata.c +5 −0 Original line number Diff line number Diff line Loading @@ -225,6 +225,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), .enable = enable_psci_bp_hardening, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_KRYO2XX_GOLD), .enable = enable_psci_bp_hardening, }, #endif { } Loading