Merge "arm64: Implement branch predictor hardening for affected Cortex-A CPUs" (049d9307) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm64/kernel/bpi.S

+24 −0

Original line number	Diff line number	Diff line
		@@ -53,3 +53,27 @@ ENTRY(__bp_harden_hyp_vecs_start)
		vectors __kvm_hyp_vector
		.endr
		ENTRY(__bp_harden_hyp_vecs_end)
		ENTRY(__psci_hyp_bp_inval_start)
		sub sp, sp, #(8 * 18)
		stp x16, x17, [sp, #(16 * 0)]
		stp x14, x15, [sp, #(16 * 1)]
		stp x12, x13, [sp, #(16 * 2)]
		stp x10, x11, [sp, #(16 * 3)]
		stp x8, x9, [sp, #(16 * 4)]
		stp x6, x7, [sp, #(16 * 5)]
		stp x4, x5, [sp, #(16 * 6)]
		stp x2, x3, [sp, #(16 * 7)]
		stp x0, x1, [sp, #(16 * 8)]
		mov x0, #0x84000000
		smc #0
		ldp x16, x17, [sp, #(16 * 0)]
		ldp x14, x15, [sp, #(16 * 1)]
		ldp x12, x13, [sp, #(16 * 2)]
		ldp x10, x11, [sp, #(16 * 3)]
		ldp x8, x9, [sp, #(16 * 4)]
		ldp x6, x7, [sp, #(16 * 5)]
		ldp x4, x5, [sp, #(16 * 6)]
		ldp x2, x3, [sp, #(16 * 7)]
		ldp x0, x1, [sp, #(16 * 8)]
		add sp, sp, #(8 * 18)
		ENTRY(__psci_hyp_bp_inval_end)

arch/arm64/kernel/cpu_errata.c

+41 −0

Original line number	Diff line number	Diff line
		@@ -36,6 +36,8 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry)
		DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);

		#ifdef CONFIG_KVM
		extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[];

		static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
		const char *hyp_vecs_end)
		{
		@@ -77,6 +79,8 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
		spin_unlock(&bp_lock);
		}
		#else
		#define __psci_hyp_bp_inval_start NULL
		#define __psci_hyp_bp_inval_end NULL

		static void __maybe_unused __install_bp_hardening_cb(bp_hardening_cb_t fn,
		const char *hyp_vecs_start,
		@@ -103,6 +107,21 @@ static void __maybe_unused install_bp_hardening_cb(

		__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
		}

		#include <linux/psci.h>

		static int enable_psci_bp_hardening(void *data)
		{
		const struct arm64_cpu_capabilities *entry = data;

		if (psci_ops.get_version)
		install_bp_hardening_cb(entry,
		(bp_hardening_cb_t)psci_ops.get_version,
		__psci_hyp_bp_inval_start,
		__psci_hyp_bp_inval_end);

		return 0;
		}
		#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */

		#define MIDR_RANGE(model, min, max) \
		@@ -184,6 +203,28 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
		MIDR_RANGE(MIDR_THUNDERX, 0x00,
		(1 << MIDR_VARIANT_SHIFT) \| 1),
		},
		#endif
		#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
		{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
		.enable = enable_psci_bp_hardening,
		},
		{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
		.enable = enable_psci_bp_hardening,
		},
		{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
		.enable = enable_psci_bp_hardening,
		},
		{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
		.enable = enable_psci_bp_hardening,
		},
		#endif
		{
		}