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Commit e245f54a authored by Laxman Dewangan's avatar Laxman Dewangan Committed by Stephen Warren
Browse files

ARM: tegra: Add OF_DEV_AUXDATA for sflash driver in board dt 



Add OF_DEV_AUXDATA for sflash controller driver for Tegra20
board dt files.
Set the parent clock of sflash controller to PLLP and configure
clock to 20MHz.

Signed-off-by: default avatarLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent ca3d241c

arch/arm/mach-tegra/board-dt-tegra20.c

+2 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 
		       &tegra_ehci3_pdata),

	OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
@@ -112,6 +113,7 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { 
	{ "sdmmc1",	"pll_p",	48000000,	false},

	{ "sdmmc3",	"pll_p",	48000000,	false},

	{ "sdmmc4",	"pll_p",	48000000,	false},

	{ "spi",	"pll_p",	20000000,	false },

	{ "sbc1",	"pll_p",	100000000,	false },

	{ "sbc2",	"pll_p",	100000000,	false },

	{ "sbc3",	"pll_p",	100000000,	false },