Merge "clk: qcom: update post div bits to be cleared for MMCC/GPU clocks" (dbba2248) · Commits · e / devices / android_kernel_sony_msm8998

drivers/clk/qcom/common.c

+19 −2

Original line number	Diff line number	Diff line
		@@ -334,16 +334,17 @@ static u32 run_measurement(unsigned ticks, struct regmap *regmap,
		static unsigned long clk_debug_mux_measure_rate(struct clk_hw *hw)
		{
		unsigned long flags, ret = 0;
		u32 gcc_xo4_reg, sample_ticks = 0x10000, multiplier = 1;
		u32 gcc_xo4_reg, sample_ticks = 0x10000, multiplier;
		u64 raw_count_short, raw_count_full;
		struct clk_debug_mux *meas = to_clk_measure(hw);
		struct measure_clk_data *data = meas->priv;


		clk_prepare_enable(data->cxo);

		spin_lock_irqsave(&clk_reg_lock, flags);

		multiplier = meas->multiplier + 1;

		/* Enable CXO/4 and RINGOSC branch. */
		regmap_read(meas->regmap[GCC], data->xo_div4_cbcr, &gcc_xo4_reg);
		gcc_xo4_reg \|= BIT(0);
		@@ -404,6 +405,7 @@ static u8 clk_debug_mux_get_parent(struct clk_hw *hw)
		static int clk_debug_mux_set_parent(struct clk_hw *hw, u8 index)
		{
		struct clk_debug_mux *meas = to_clk_measure(hw);
		unsigned long lsb = 0;
		u32 regval = 0;
		int dbg_cc = 0;

		@@ -412,6 +414,16 @@ static int clk_debug_mux_set_parent(struct clk_hw *hw, u8 index)
		if (dbg_cc != GCC) {
		regmap_read(meas->regmap[dbg_cc], 0x0, &regval);

		/* Clear & Set post divider bits */
		if (meas->parent[index].post_div_mask) {
		regval &= ~meas->parent[index].post_div_mask;
		lsb = find_first_bit((unsigned long *)
		&meas->parent[index].post_div_mask, 32);
		regval \|= (meas->parent[index].post_div_val << lsb) &
		meas->parent[index].post_div_mask;
		meas->multiplier = meas->parent[index].post_div_val;
		}

		if (meas->parent[index].mask)
		regval &= ~meas->parent[index].mask <<
		meas->parent[index].shift;
		@@ -436,6 +448,11 @@ static int clk_debug_mux_set_parent(struct clk_hw *hw, u8 index)

		/* clear post divider bits */
		regval &= ~BM(15, 12);
		lsb = find_first_bit((unsigned long *)
		&meas->parent[index].post_div_mask, 32);
		regval \|= (meas->parent[index].post_div_val << lsb) &
		meas->parent[index].post_div_mask;
		meas->multiplier = meas->parent[index].post_div_val;
		regval &= ~meas->mask;
		regval \|= (meas->parent[index].sel & meas->mask);
		regval \|= meas->en_mask;

drivers/clk/qcom/common.h

+11 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
		* Copyright (c) 2014, 2016-2017, The Linux Foundation. All rights reserved.
		*
		* This software is licensed under the terms of the GNU General Public
		* License version 2, as published by the Free Software Foundation, and
		@@ -94,6 +94,10 @@ enum debug_cc {
		* Incase the recursive debug mux does not have a enable bit,
		* 0xFF should be used to indicate the same, otherwise global
		* enable bit would be used.
		* @post_div_mask: indicates the post div mask to be used at debug/recursive
		* debug mux.
		* @post_div_val: indicates the post div value to be used at debug/recursive
		* debug mux.
		*/
		struct clk_src {
		const char *parents;
		@@ -103,6 +107,8 @@ struct clk_src {
		u32 mask;
		u32 shift;
		u32 en_mask;
		u32 post_div_mask;
		u32 post_div_val;
		};

		#define MUX_SRC_LIST(...) \
		@@ -123,6 +129,7 @@ struct clk_src {
		* controller debug mux.
		* @debug_offset: Start of debug mux offset.
		* @hw: handle between common and hardware-specific interfaces.
		* @multiplier: internally used by debug mux as post div multiplier.
		*/
		struct clk_debug_mux {
		struct clk_src *parent;
		@@ -134,6 +141,9 @@ struct clk_debug_mux {
		u32 mask;
		u32 debug_offset;
		struct clk_hw hw;

		/* internal */
		u32 multiplier;
		};

		#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)

drivers/clk/qcom/gcc-sdm660.c

+93 −90

Original line number	Diff line number	Diff line
		@@ -3098,182 +3098,185 @@ static struct clk_debug_mux gcc_debug_mux = {
		{ "gcc_ufs_tx_symbol_0_clk", 0x0EC },
		{ "gcc_usb3_phy_pipe_clk", 0x040 },
		{ "mmssnoc_axi_clk", 0x22, MMCC,
		0x004, 0, 0, 0x1000 },
		0x004, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_bimc_smmu_ahb_clk", 0x22, MMCC,
		0x00C, 0, 0, 0x1000 },
		0x00C, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_bimc_smmu_axi_clk", 0x22, MMCC,
		0x00D, 0, 0, 0x1000 },
		0x00D, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_ahb_clk", 0x22, MMCC,
		0x037, 0, 0, 0x1000 },
		0x037, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cci_ahb_clk", 0x22, MMCC,
		0x02E, 0, 0, 0x1000 },
		0x02E, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cci_clk", 0x22, MMCC,
		0x02D, 0, 0, 0x1000 },
		0x02D, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cphy_csid0_clk", 0x22, MMCC,
		0x08D, 0, 0, 0x1000 },
		0x08D, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cphy_csid1_clk", 0x22, MMCC,
		0x08E, 0, 0, 0x1000 },
		0x08E, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cphy_csid2_clk", 0x22, MMCC,
		0x08F, 0, 0, 0x1000 },
		0x08F, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cphy_csid3_clk", 0x22, MMCC,
		0x090, 0, 0, 0x1000 },
		0x090, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cpp_ahb_clk", 0x22, MMCC,
		0x03B, 0, 0, 0x1000 },
		0x03B, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cpp_axi_clk", 0x22, MMCC,
		0x07A, 0, 0, 0x1000 },
		0x07A, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cpp_clk", 0x22, MMCC,
		0x03A, 0, 0, 0x1000 },
		0x03A, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_cpp_vbif_ahb_clk", 0x22, MMCC,
		0x073, 0, 0, 0x1000 },
		0x073, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi0_ahb_clk", 0x22, MMCC,
		0x042, 0, 0, 0x1000 },
		0x042, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi0_clk", 0x22, MMCC,
		0x041, 0, 0, 0x1000 },
		0x041, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi0phytimer_clk", 0x22, MMCC,
		0x02F, 0, 0, 0x1000 },
		0x02F, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi0pix_clk", 0x22, MMCC,
		0x045, 0, 0, 0x1000 },
		0x045, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi0rdi_clk", 0x22, MMCC,
		0x044, 0, 0, 0x1000 },
		0x044, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi1_ahb_clk", 0x22, MMCC,
		0x047, 0, 0, 0x1000 },
		0x047, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi1_clk", 0x22, MMCC,
		0x046, 0, 0, 0x1000 },
		0x046, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi1phytimer_clk", 0x22, MMCC,
		0x030, 0, 0, 0x1000 },
		0x030, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi1pix_clk", 0x22, MMCC,
		0x04A, 0, 0, 0x1000 },
		0x04A, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi1rdi_clk", 0x22, MMCC,
		0x049, 0, 0, 0x1000 },
		0x049, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi2_ahb_clk", 0x22, MMCC,
		0x04C, 0, 0, 0x1000 },
		0x04C, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi2_clk", 0x22, MMCC,
		0x04B, 0, 0, 0x1000 },
		0x04B, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi2phytimer_clk", 0x22, MMCC,
		0x031, 0, 0, 0x1000 },
		0x031, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi2pix_clk", 0x22, MMCC,
		0x04F, 0, 0, 0x1000 },
		0x04F, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi2rdi_clk", 0x22, MMCC,
		0x04E, 0, 0, 0x1000 },
		0x04E, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi3_ahb_clk", 0x22, MMCC,
		0x051, 0, 0, 0x1000 },
		0x051, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi3_clk", 0x22, MMCC,
		0x050, 0, 0, 0x1000 },
		0x050, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi3pix_clk", 0x22, MMCC,
		0x054, 0, 0, 0x1000 },
		0x054, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi3rdi_clk", 0x22, MMCC,
		0x053, 0, 0, 0x1000 },
		0x053, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi_vfe0_clk", 0x22, MMCC,
		0x03F, 0, 0, 0x1000 },
		0x03F, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csi_vfe1_clk", 0x22, MMCC,
		0x040, 0, 0, 0x1000 },
		0x040, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csiphy0_clk", 0x22, MMCC,
		0x043, 0, 0, 0x1000 },
		0x043, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csiphy1_clk", 0x22, MMCC,
		0x085, 0, 0, 0x1000 },
		0x085, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_csiphy2_clk", 0x22, MMCC,
		0x088, 0, 0, 0x1000 },
		0x088, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_gp0_clk", 0x22, MMCC,
		0x027, 0, 0, 0x1000 },
		0x027, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_gp1_clk", 0x22, MMCC,
		0x028, 0, 0, 0x1000 },
		0x028, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_ispif_ahb_clk", 0x22, MMCC,
		0x033, 0, 0, 0x1000 },
		0x033, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_jpeg0_clk", 0x22, MMCC,
		0x032, 0, 0, 0x1000 },
		0x032, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_jpeg_ahb_clk", 0x22, MMCC,
		0x035, 0, 0, 0x1000 },
		0x035, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_jpeg_axi_clk", 0x22, MMCC,
		0x036, 0, 0, 0x1000 },
		0x036, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_mclk0_clk", 0x22, MMCC,
		0x029, 0, 0, 0x1000 },
		0x029, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_mclk1_clk", 0x22, MMCC,
		0x02A, 0, 0, 0x1000 },
		0x02A, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_mclk2_clk", 0x22, MMCC,
		0x02B, 0, 0, 0x1000 },
		0x02B, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_mclk3_clk", 0x22, MMCC,
		0x02C, 0, 0, 0x1000 },
		0x02C, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_micro_ahb_clk", 0x22, MMCC,
		0x026, 0, 0, 0x1000 },
		0x026, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_top_ahb_clk", 0x22, MMCC,
		0x025, 0, 0, 0x1000 },
		0x025, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_vfe0_ahb_clk", 0x22, MMCC,
		0x086, 0, 0, 0x1000 },
		0x086, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_vfe0_clk", 0x22, MMCC,
		0x038, 0, 0, 0x1000 },
		0x038, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_vfe0_stream_clk", 0x22, MMCC,
		0x071, 0, 0, 0x1000 },
		0x071, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_vfe1_ahb_clk", 0x22, MMCC,
		0x087, 0, 0, 0x1000 },
		0x087, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_vfe1_clk", 0x22, MMCC,
		0x039, 0, 0, 0x1000 },
		0x039, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_vfe1_stream_clk", 0x22, MMCC,
		0x072, 0, 0, 0x1000 },
		0x072, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_vfe_vbif_ahb_clk", 0x22, MMCC,
		0x03C, 0, 0, 0x1000 },
		0x03C, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_camss_vfe_vbif_axi_clk", 0x22, MMCC,
		0x03D, 0, 0, 0x1000 },
		0x03D, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_csiphy_ahb2crif_clk", 0x22, MMCC,
		0x0B8, 0, 0, 0x1000 },
		0x0B8, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_ahb_clk", 0x22, MMCC,
		0x022, 0, 0, 0x1000 },
		0x022, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_axi_clk", 0x22, MMCC,
		0x024, 0, 0, 0x1000 },
		0x024, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_byte0_clk", 0x22, MMCC,
		0x01E, 0, 0, 0x1000 },
		0x01E, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_byte0_intf_clk", 0x22, MMCC,
		0x0AD, 0, 0, 0x1000 },
		0x0AD, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_byte1_clk", 0x22, MMCC,
		0x01F, 0, 0, 0x1000 },
		0x01F, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_byte1_intf_clk", 0x22, MMCC,
		0x0B6, 0, 0, 0x1000 },
		0x0B6, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_dp_aux_clk", 0x22, MMCC,
		0x09C, 0, 0, 0x1000 },
		0x09C, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_dp_crypto_clk", 0x22, MMCC,
		0x09A, 0, 0, 0x1000 },
		0x09A, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_dp_gtc_clk", 0x22, MMCC,
		0x09D, 0, 0, 0x1000 },
		0x09D, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_dp_link_clk", 0x22, MMCC,
		0x098, 0, 0, 0x1000 },
		0x098, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_dp_link_intf_clk", 0x22, MMCC,
		0x099, 0, 0, 0x1000 },
		0x099, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_dp_pixel_clk", 0x22, MMCC,
		0x09B, 0, 0, 0x1000 },
		0x09B, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_esc0_clk", 0x22, MMCC,
		0x020, 0, 0, 0x1000 },
		0x020, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_esc1_clk", 0x22, MMCC,
		0x021, 0, 0, 0x1000 },
		0x021, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_hdmi_dp_ahb_clk", 0x22, MMCC,
		0x023, 0, 0, 0x1000 },
		0x023, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_mdp_clk", 0x22, MMCC,
		0x014, 0, 0, 0x1000 },
		0x014, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_pclk0_clk", 0x22, MMCC,
		0x016, 0, 0, 0x1000 },
		0x016, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_pclk1_clk", 0x22, MMCC,
		0x017, 0, 0, 0x1000 },
		0x017, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_rot_clk", 0x22, MMCC,
		0x012, 0, 0, 0x1000 },
		0x012, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mdss_vsync_clk", 0x22, MMCC,
		0x01C, 0, 0, 0x1000 },
		0x01C, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_misc_ahb_clk", 0x22, MMCC,
		0x003, 0, 0, 0x1000 },
		0x003, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_misc_cxo_clk", 0x22, MMCC,
		0x077, 0, 0, 0x1000 },
		0x077, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_mnoc_ahb_clk", 0x22, MMCC,
		0x001, 0, 0, 0x1000 },
		0x001, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_snoc_dvm_axi_clk", 0x22, MMCC,
		0x013, 0, 0, 0x1000 },
		0x013, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_video_ahb_clk", 0x22, MMCC,
		0x011, 0, 0, 0x1000 },
		0x011, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_video_axi_clk", 0x22, MMCC,
		0x00F, 0, 0, 0x1000 },
		0x00F, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_video_core_clk", 0x22, MMCC,
		0x00E, 0, 0, 0x1000 },
		0x00E, 0, 0, 0x1000, BM(14, 13) },
		{ "mmss_video_subcore0_clk", 0x22, MMCC,
		0x01A, 0, 0, 0x1000 },
		{ "gpucc_gfx3d_clk", 0x13d, GPU, 0x008 },
		{ "gpucc_rbbmtimer_clk", 0x13d, GPU, 0x005 },
		{ "gpucc_rbcpr_clk", 0x13d, GPU, 0x003 },
		0x01A, 0, 0, 0x1000, BM(14, 13) },
		{ "gpucc_gfx3d_clk", 0x13d, GPU,
		0x008, 0, 0, 0, BM(18, 17) },
		{ "gpucc_rbbmtimer_clk", 0x13d, GPU,
		0x005, 0, 0, 0, BM(18, 17) },
		{ "gpucc_rbcpr_clk", 0x13d, GPU,
		0x003, 0, 0, 0, BM(18, 17) },
		{ "pwrcl_clk", 0x0c0, CPU, 0x000, 0x3, 8, 0x0FF },
		{ "perfcl_clk", 0x0c0, CPU, 0x100, 0x3, 8, 0x0FF },
		),