Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit aff127cb authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: update post div bits to be cleared for MMCC/GPU clocks 



MMCC and GPU clocks needs the post div bits to be cleared, so that the
clock measure does not account for any previously set div values in the
debug mux.

Change-Id: I1123e566740518e287692797fa3ab6b316da3bf1
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent f2b160b4

drivers/clk/qcom/gcc-sdm660.c

+93 −90
Original line number Diff line number Diff line
@@ -3109,182 +3109,185 @@ static struct clk_debug_mux gcc_debug_mux = { 
		{ "gcc_ufs_tx_symbol_0_clk",		0x0EC },

		{ "gcc_usb3_phy_pipe_clk",		0x040 },

		{ "mmssnoc_axi_clk",	0x22,   MMCC,

						0x004, 0, 0, 0x1000 },

					0x004, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_bimc_smmu_ahb_clk", 0x22,	MMCC,

						0x00C, 0, 0, 0x1000 },

					0x00C, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_bimc_smmu_axi_clk",	0x22,	MMCC,

						0x00D, 0, 0, 0x1000 },

					0x00D, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_ahb_clk",		0x22,	MMCC,

						0x037, 0, 0, 0x1000 },

					0x037, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cci_ahb_clk",	0x22,	MMCC,

						0x02E, 0, 0, 0x1000 },

					0x02E, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cci_clk",		0x22,	MMCC,

						0x02D, 0, 0, 0x1000 },

					0x02D, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cphy_csid0_clk",	0x22,	MMCC,

						0x08D, 0, 0, 0x1000 },

					0x08D, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cphy_csid1_clk",	0x22,	MMCC,

						0x08E, 0, 0, 0x1000 },

					0x08E, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cphy_csid2_clk",	0x22,	MMCC,

						0x08F, 0, 0, 0x1000 },

					0x08F, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cphy_csid3_clk",	0x22,	MMCC,

						0x090, 0, 0, 0x1000 },

					0x090, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cpp_ahb_clk",	0x22,	MMCC,

						0x03B, 0, 0, 0x1000 },

					0x03B, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cpp_axi_clk",	0x22,	MMCC,

						0x07A, 0, 0, 0x1000 },

					0x07A, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cpp_clk",		0x22,	MMCC,

						0x03A, 0, 0, 0x1000 },

					0x03A, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_cpp_vbif_ahb_clk", 0x22,	MMCC,

						0x073, 0, 0, 0x1000 },

					0x073, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi0_ahb_clk",	0x22,	MMCC,

						0x042, 0, 0, 0x1000 },

					0x042, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi0_clk",	0x22,	MMCC,

						0x041, 0, 0, 0x1000 },

					0x041, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi0phytimer_clk", 0x22,	MMCC,

						0x02F, 0, 0, 0x1000 },

					0x02F, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi0pix_clk",	0x22,	MMCC,

						0x045, 0, 0, 0x1000 },

					0x045, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi0rdi_clk",	0x22,	MMCC,

						0x044, 0, 0, 0x1000 },

					0x044, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi1_ahb_clk",	0x22,	MMCC,

						0x047, 0, 0, 0x1000 },

					0x047, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi1_clk",	0x22,	MMCC,

						0x046, 0, 0, 0x1000 },

					0x046, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi1phytimer_clk", 0x22,	MMCC,

						0x030, 0, 0, 0x1000 },

					0x030, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi1pix_clk",	0x22,	MMCC,

						0x04A, 0, 0, 0x1000 },

					0x04A, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi1rdi_clk",	0x22,	MMCC,

						0x049, 0, 0, 0x1000 },

					0x049, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi2_ahb_clk",	0x22,	MMCC,

						0x04C, 0, 0, 0x1000 },

					0x04C, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi2_clk",	0x22,	MMCC,

						0x04B, 0, 0, 0x1000 },

					0x04B, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi2phytimer_clk", 0x22,	MMCC,

						0x031, 0, 0, 0x1000 },

					0x031, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi2pix_clk",	0x22,	MMCC,

						0x04F, 0, 0, 0x1000 },

					0x04F, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi2rdi_clk",	0x22,	MMCC,

						0x04E, 0, 0, 0x1000 },

					0x04E, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi3_ahb_clk",	0x22,	MMCC,

						0x051, 0, 0, 0x1000 },

					0x051, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi3_clk",	0x22,	MMCC,

						0x050, 0, 0, 0x1000 },

					0x050, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi3pix_clk",	0x22,   MMCC,

						0x054, 0, 0, 0x1000 },

					0x054, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi3rdi_clk",	0x22,	MMCC,

						0x053, 0, 0, 0x1000 },

					0x053, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi_vfe0_clk",	0x22,	MMCC,

						0x03F, 0, 0, 0x1000 },

					0x03F, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csi_vfe1_clk",	0x22,	MMCC,

						0x040, 0, 0, 0x1000 },

					0x040, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csiphy0_clk",	0x22,	MMCC,

						0x043, 0, 0, 0x1000 },

					0x043, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csiphy1_clk",	0x22,	MMCC,

						0x085, 0, 0, 0x1000 },

					0x085, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_csiphy2_clk",	0x22,	MMCC,

						0x088, 0, 0, 0x1000 },

					0x088, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_gp0_clk",		0x22,	MMCC,

						0x027, 0, 0, 0x1000 },

					0x027, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_gp1_clk",		0x22,	MMCC,

						0x028, 0, 0, 0x1000 },

					0x028, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_ispif_ahb_clk",	0x22,	MMCC,

						0x033, 0, 0, 0x1000 },

					0x033, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_jpeg0_clk",	0x22,	MMCC,

						0x032, 0, 0, 0x1000 },

					0x032, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_jpeg_ahb_clk",	0x22,	MMCC,

						0x035, 0, 0, 0x1000 },

					0x035, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_jpeg_axi_clk",	0x22,	MMCC,

						0x036, 0, 0, 0x1000 },

					0x036, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_mclk0_clk",	0x22,	MMCC,

						0x029, 0, 0, 0x1000 },

					0x029, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_mclk1_clk",	0x22,	MMCC,

						0x02A, 0, 0, 0x1000 },

					0x02A, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_mclk2_clk",	0x22,	MMCC,

						0x02B, 0, 0, 0x1000 },

					0x02B, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_mclk3_clk",	0x22,	MMCC,

						0x02C, 0, 0, 0x1000 },

					0x02C, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_micro_ahb_clk",	0x22,	MMCC,

						0x026, 0, 0, 0x1000 },

					0x026, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_top_ahb_clk",	0x22,	MMCC,

						0x025, 0, 0, 0x1000 },

					0x025, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_vfe0_ahb_clk",	0x22,	MMCC,

						0x086, 0, 0, 0x1000 },

					0x086, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_vfe0_clk",	0x22,	MMCC,

						0x038, 0, 0, 0x1000 },

					0x038, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_vfe0_stream_clk",	0x22,	MMCC,

						0x071, 0, 0, 0x1000 },

					0x071, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_vfe1_ahb_clk",	0x22,	MMCC,

						0x087, 0, 0, 0x1000 },

					0x087, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_vfe1_clk",	0x22,	MMCC,

						0x039, 0, 0, 0x1000 },

					0x039, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_vfe1_stream_clk",	0x22,	MMCC,

						0x072, 0, 0, 0x1000 },

					0x072, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_vfe_vbif_ahb_clk", 0x22,	MMCC,

						0x03C, 0, 0, 0x1000 },

					0x03C, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_camss_vfe_vbif_axi_clk", 0x22,	MMCC,

						0x03D, 0, 0, 0x1000 },

					0x03D, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_csiphy_ahb2crif_clk",	0x22,	MMCC,

						0x0B8, 0, 0, 0x1000 },

					0x0B8, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_ahb_clk",		0x22,	MMCC,

						0x022, 0, 0, 0x1000 },

					0x022, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_axi_clk",		0x22,	MMCC,

						0x024, 0, 0, 0x1000 },

					0x024, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_byte0_clk",	0x22,	MMCC,

						0x01E, 0, 0, 0x1000 },

					0x01E, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_byte0_intf_clk",	0x22,	MMCC,

						0x0AD, 0, 0, 0x1000 },

					0x0AD, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_byte1_clk",	0x22,	MMCC,

						0x01F, 0, 0, 0x1000 },

					0x01F, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_byte1_intf_clk",	0x22,	MMCC,

						0x0B6, 0, 0, 0x1000 },

					0x0B6, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_dp_aux_clk",	0x22,	MMCC,

						0x09C, 0, 0, 0x1000 },

					0x09C, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_dp_crypto_clk",	0x22,	MMCC,

						0x09A, 0, 0, 0x1000 },

					0x09A, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_dp_gtc_clk",	0x22,	MMCC,

						0x09D, 0, 0, 0x1000 },

					0x09D, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_dp_link_clk",	0x22,	MMCC,

						0x098, 0, 0, 0x1000 },

					0x098, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_dp_link_intf_clk",	0x22,	MMCC,

						0x099, 0, 0, 0x1000 },

					0x099, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_dp_pixel_clk",	0x22,	MMCC,

						0x09B, 0, 0, 0x1000 },

					0x09B, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_esc0_clk",		0x22,	MMCC,

						0x020, 0, 0, 0x1000 },

					0x020, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_esc1_clk",		0x22,	MMCC,

						0x021, 0, 0, 0x1000 },

					0x021, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_hdmi_dp_ahb_clk",	0x22,	MMCC,

						0x023, 0, 0, 0x1000 },

					0x023, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_mdp_clk",		0x22,	MMCC,

						0x014, 0, 0, 0x1000 },

					0x014, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_pclk0_clk",	0x22,	MMCC,

						0x016, 0, 0, 0x1000 },

					0x016, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_pclk1_clk",	0x22,	MMCC,

						0x017, 0, 0, 0x1000 },

					0x017, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_rot_clk",		0x22,	MMCC,

						0x012, 0, 0, 0x1000 },

					0x012, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mdss_vsync_clk",	0x22,	MMCC,

						0x01C, 0, 0, 0x1000 },

					0x01C, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_misc_ahb_clk",		0x22,	MMCC,

						0x003, 0, 0, 0x1000 },

					0x003, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_misc_cxo_clk",		0x22,	MMCC,

						0x077, 0, 0, 0x1000 },

					0x077, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_mnoc_ahb_clk",		0x22,	MMCC,

						0x001, 0, 0, 0x1000 },

					0x001, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_snoc_dvm_axi_clk",	0x22,	MMCC,

						0x013, 0, 0, 0x1000 },

					0x013, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_video_ahb_clk",		0x22,	MMCC,

						0x011, 0, 0, 0x1000 },

					0x011, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_video_axi_clk",		0x22,	MMCC,

						0x00F, 0, 0, 0x1000 },

					0x00F, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_video_core_clk",	0x22,	MMCC,

						0x00E, 0, 0, 0x1000 },

					0x00E, 0, 0, 0x1000, BM(14, 13) },

		{ "mmss_video_subcore0_clk",	0x22,	MMCC,

						0x01A, 0, 0, 0x1000 },

		{ "gpucc_gfx3d_clk",		0x13d,	GPU, 0x008 },

		{ "gpucc_rbbmtimer_clk",	0x13d,	GPU, 0x005 },

		{ "gpucc_rbcpr_clk",		0x13d,	GPU, 0x003 },

					0x01A, 0, 0, 0x1000, BM(14, 13) },

		{ "gpucc_gfx3d_clk",		0x13d,	GPU,

					0x008, 0, 0, 0, BM(18, 17) },

		{ "gpucc_rbbmtimer_clk",	0x13d,	GPU,

					0x005, 0, 0, 0, BM(18, 17) },

		{ "gpucc_rbcpr_clk",		0x13d,	GPU,

					0x003, 0, 0, 0, BM(18, 17) },

		{ "pwrcl_clk",	0x0c0,	CPU,	0x000,	0x3, 8,	0x0FF },

		{ "perfcl_clk",	0x0c0,	CPU,	0x100,	0x3, 8,	0x0FF },

	),