Loading arch/arm/boot/dts/qcom/sdm660.dtsi +4 −2 Original line number Original line Diff line number Diff line Loading @@ -1276,8 +1276,10 @@ 100000000 200000000 400000000 4294967295>; 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>; <&clock_gcc GCC_SDCC1_APPS_CLK>, clock-names = "iface_clk", "core_clk"; <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface_clk", "core_clk", "ice_core_clk"; qcom,ice-clk-rates = <300000000 150000000>; status = "disabled"; status = "disabled"; }; }; Loading Loading
arch/arm/boot/dts/qcom/sdm660.dtsi +4 −2 Original line number Original line Diff line number Diff line Loading @@ -1276,8 +1276,10 @@ 100000000 200000000 400000000 4294967295>; 100000000 200000000 400000000 4294967295>; clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>; <&clock_gcc GCC_SDCC1_APPS_CLK>, clock-names = "iface_clk", "core_clk"; <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface_clk", "core_clk", "ice_core_clk"; qcom,ice-clk-rates = <300000000 150000000>; status = "disabled"; status = "disabled"; }; }; Loading