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Commit cfc75ed6 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge branch 'pm-cpufreq' 

* pm-cpufreq: (21 commits)
  intel_pstate: skip this driver if Sun server has _PPC method
  cpufreq: arm_big_little: free OPP table created during ->init()
  imx6q: free OPP table created during ->init()
  exynos5440: free OPP table created during ->init()
  cpufreq-dt: free OPP table created during ->init()
  cpufreq-dt: register cooling device from ->ready() callback
  cpufreq: Introduce ->ready() callback for cpufreq drivers
  cpufreq-dt: pass 'policy->related_cpus' to of_cpufreq_cooling_register()
  cpufreq: Fix formatting issues in 'struct cpufreq_driver'
  cpufreq: pxa2xx: Add Kconfig entry
  cpufreq: Ref the policy object sooner
  cpufreq: Kconfig: Remove architecture specific menu entries
  cpufreq: pcc: Enable autoload of pcc-cpufreq for ACPI processors
  intel_pstate: Add CPUID for BDW-H CPU
  intel_pstate: Add support for HWP
  x86: Add support for Intel HWP feature detection.
  cpufreq: respect the min/max settings from user space
  cpufreq: cpufreq-dt: Handle regulator_get_voltage() failure
  cpufreq: cpufreq-dt: Improve debug about matching OPP
  cpufreq: Loongson1: Add cpufreq driver for Loongson1B
  ...
parents 648fcab2 966916ea

Documentation/cpu-freq/intel-pstate.txt

+25 −12
Original line number Original line Diff line number Diff line 
Intel P-state driver

Intel P-state driver

--------------------

--------------------





This driver implements a scaling driver with an internal governor for

This driver provides an interface to control the P state selection for

Intel Core processors.  The driver follows the same model as the

SandyBridge+ Intel processors.  The driver can operate two different

Transmeta scaling driver (longrun.c) and implements the setpolicy()

modes based on the processor model legacy and Hardware P state (HWP)

instead of target().  Scaling drivers that implement setpolicy() are

mode.

assumed to implement internal governors by the cpufreq core. All the



logic for selecting the current P state is contained within the

In legacy mode the driver implements a scaling driver with an internal

driver; no external governor is used by the cpufreq core.

governor for Intel Core processors.  The driver follows the same model



as the Transmeta scaling driver (longrun.c) and implements the

Intel SandyBridge+ processors are supported.

setpolicy() instead of target().  Scaling drivers that implement



setpolicy() are assumed to implement internal governors by the cpufreq

New sysfs files for controlling P state selection have been added to

core. All the logic for selecting the current P state is contained

within the driver; no external governor is used by the cpufreq core.



In HWP mode P state selection is implemented in the processor

itself. The driver provides the interfaces between the cpufreq core and

the processor to control P state selection based on user preferences

and reporting frequency to the cpufreq core.  In this mode the

internal governor code is disabled.



In addtion to the interfaces provided by the cpufreq core for

controlling frequency the driver provides sysfs files for

controlling P state selection. These files have been added to

/sys/devices/system/cpu/intel_pstate/

/sys/devices/system/cpu/intel_pstate/





      max_perf_pct: limits the maximum P state that will be requested by

      max_perf_pct: limits the maximum P state that will be requested by
@@ -33,7 +44,9 @@ frequency is fiction for Intel Core processors. Even if the scaling 
driver selects a single P state the actual frequency the processor

driver selects a single P state the actual frequency the processor

will run at is selected by the processor itself.

will run at is selected by the processor itself.





New debugfs files have also been added to /sys/kernel/debug/pstate_snb/

For legacy mode debugfs files have also been added to allow tuning of

the internal governor algorythm. These files are located at

/sys/kernel/debug/pstate_snb/ These files are NOT present in HWP mode.





      deadband

      deadband

      d_gain_pct

      d_gain_pct

Documentation/kernel-parameters.txt

+3 −0
Original line number Original line Diff line number Diff line
@@ -1446,6 +1446,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 
		       disable

		       disable

		         Do not enable intel_pstate as the default

		         Do not enable intel_pstate as the default

		         scaling driver for the supported processors

		         scaling driver for the supported processors

		       no_hwp

		         Do not enable hardware P state control (HWP)

			 if available.





	intremap=	[X86-64, Intel-IOMMU]

	intremap=	[X86-64, Intel-IOMMU]

			on	enable Interrupt Remapping (default)

			on	enable Interrupt Remapping (default)

arch/x86/include/asm/cpufeature.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -189,6 +189,11 @@ 
#define X86_FEATURE_DTHERM	( 7*32+ 7) /* Digital Thermal Sensor */

#define X86_FEATURE_DTHERM	( 7*32+ 7) /* Digital Thermal Sensor */

#define X86_FEATURE_HW_PSTATE	( 7*32+ 8) /* AMD HW-PState */

#define X86_FEATURE_HW_PSTATE	( 7*32+ 8) /* AMD HW-PState */

#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */

#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */

#define X86_FEATURE_HWP		( 7*32+ 10) /* "hwp" Intel HWP */

#define X86_FEATURE_HWP_NOITFY	( 7*32+ 11) /* Intel HWP_NOTIFY */

#define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */

#define X86_FEATURE_HWP_EPP	( 7*32+13) /* Intel HWP_EPP */

#define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */





/* Virtualization flags: Linux defined, word 8 */

/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */

#define X86_FEATURE_TPR_SHADOW  ( 8*32+ 0) /* Intel TPR Shadow */

arch/x86/include/uapi/asm/msr-index.h

+41 −0
Original line number Original line Diff line number Diff line
@@ -152,6 +152,45 @@ 
#define MSR_CC6_DEMOTION_POLICY_CONFIG	0x00000668

#define MSR_CC6_DEMOTION_POLICY_CONFIG	0x00000668

#define MSR_MC6_DEMOTION_POLICY_CONFIG	0x00000669

#define MSR_MC6_DEMOTION_POLICY_CONFIG	0x00000669





/* Hardware P state interface */

#define MSR_PPERF			0x0000064e

#define MSR_PERF_LIMIT_REASONS		0x0000064f

#define MSR_PM_ENABLE			0x00000770

#define MSR_HWP_CAPABILITIES		0x00000771

#define MSR_HWP_REQUEST_PKG		0x00000772

#define MSR_HWP_INTERRUPT		0x00000773

#define MSR_HWP_REQUEST 		0x00000774

#define MSR_HWP_STATUS			0x00000777



/* CPUID.6.EAX */

#define HWP_BASE_BIT			(1<<7)

#define HWP_NOTIFICATIONS_BIT		(1<<8)

#define HWP_ACTIVITY_WINDOW_BIT		(1<<9)

#define HWP_ENERGY_PERF_PREFERENCE_BIT	(1<<10)

#define HWP_PACKAGE_LEVEL_REQUEST_BIT	(1<<11)



/* IA32_HWP_CAPABILITIES */

#define HWP_HIGHEST_PERF(x)		(x & 0xff)

#define HWP_GUARANTEED_PERF(x)		((x & (0xff << 8)) >>8)

#define HWP_MOSTEFFICIENT_PERF(x)	((x & (0xff << 16)) >>16)

#define HWP_LOWEST_PERF(x)		((x & (0xff << 24)) >>24)



/* IA32_HWP_REQUEST */

#define HWP_MIN_PERF(x) 		(x & 0xff)

#define HWP_MAX_PERF(x) 		((x & 0xff) << 8)

#define HWP_DESIRED_PERF(x)		((x & 0xff) << 16)

#define HWP_ENERGY_PERF_PREFERENCE(x)	((x & 0xff) << 24)

#define HWP_ACTIVITY_WINDOW(x)		((x & 0xff3) << 32)

#define HWP_PACKAGE_CONTROL(x)		((x & 0x1) << 42)



/* IA32_HWP_STATUS */

#define HWP_GUARANTEED_CHANGE(x)	(x & 0x1)

#define HWP_EXCURSION_TO_MINIMUM(x)	(x & 0x4)



/* IA32_HWP_INTERRUPT */

#define HWP_CHANGE_TO_GUARANTEED_INT(x)	(x & 0x1)

#define HWP_EXCURSION_TO_MINIMUM_INT(x)	(x & 0x2)



#define MSR_AMD64_MC0_MASK		0xc0010044

#define MSR_AMD64_MC0_MASK		0xc0010044





#define MSR_IA32_MCx_CTL(x)		(MSR_IA32_MC0_CTL + 4*(x))

#define MSR_IA32_MCx_CTL(x)		(MSR_IA32_MC0_CTL + 4*(x))
@@ -345,6 +384,8 @@ 




#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2

#define MSR_IA32_TEMPERATURE_TARGET	0x000001a2





#define MSR_MISC_PWR_MGMT		0x000001aa



#define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0

#define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0

#define ENERGY_PERF_BIAS_PERFORMANCE	0

#define ENERGY_PERF_BIAS_PERFORMANCE	0

#define ENERGY_PERF_BIAS_NORMAL		6

#define ENERGY_PERF_BIAS_NORMAL		6

arch/x86/kernel/cpu/scattered.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -36,6 +36,11 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) 
		{ X86_FEATURE_ARAT,		CR_EAX, 2, 0x00000006, 0 },

		{ X86_FEATURE_ARAT,		CR_EAX, 2, 0x00000006, 0 },

		{ X86_FEATURE_PLN,		CR_EAX, 4, 0x00000006, 0 },

		{ X86_FEATURE_PLN,		CR_EAX, 4, 0x00000006, 0 },

		{ X86_FEATURE_PTS,		CR_EAX, 6, 0x00000006, 0 },

		{ X86_FEATURE_PTS,		CR_EAX, 6, 0x00000006, 0 },

		{ X86_FEATURE_HWP,		CR_EAX, 7, 0x00000006, 0 },

		{ X86_FEATURE_HWP_NOITFY,	CR_EAX, 8, 0x00000006, 0 },

		{ X86_FEATURE_HWP_ACT_WINDOW,	CR_EAX, 9, 0x00000006, 0 },

		{ X86_FEATURE_HWP_EPP,		CR_EAX,10, 0x00000006, 0 },

		{ X86_FEATURE_HWP_PKG_REQ,	CR_EAX,11, 0x00000006, 0 },

		{ X86_FEATURE_APERFMPERF,	CR_ECX, 0, 0x00000006, 0 },

		{ X86_FEATURE_APERFMPERF,	CR_ECX, 0, 0x00000006, 0 },

		{ X86_FEATURE_EPB,		CR_ECX, 3, 0x00000006, 0 },

		{ X86_FEATURE_EPB,		CR_ECX, 3, 0x00000006, 0 },

		{ X86_FEATURE_HW_PSTATE,	CR_EDX, 7, 0x80000007, 0 },

		{ X86_FEATURE_HW_PSTATE,	CR_EDX, 7, 0x80000007, 0 },