Loading Documentation/devicetree/bindings/cnss/icnss.txt +2 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,7 @@ Required properties: Optional properties: - qcom,icnss-vadc: VADC handle for vph_pwr read APIs. - qcom,icnss-adc_tm: VADC handle for vph_pwr notification APIs. - qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass Example: Loading @@ -43,4 +44,5 @@ Example: <0 140 0 /* CE10 */ >, <0 141 0 /* CE11 */ >; qcom,wlan-msa-memory = <0x200000>; qcom,smmu-s1-bypass; }; arch/arm/boot/dts/qcom/sdm630.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1458,6 +1458,7 @@ <0 424 0>, /* CE10 */ <0 425 0>; /* CE11 */ qcom,wlan-msa-memory = <0x100000>; qcom,smmu-s1-bypass; }; qcom,lpass@15700000 { Loading arch/arm/boot/dts/qcom/sdm660.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1891,6 +1891,7 @@ <0 424 0>, /* CE10 */ <0 425 0>; /* CE11 */ qcom,wlan-msa-memory = <0x100000>; qcom,smmu-s1-bypass; }; qcom,lpass@15700000 { Loading drivers/soc/qcom/icnss.c +15 −7 Original line number Diff line number Diff line Loading @@ -334,6 +334,7 @@ static struct icnss_priv { struct ramdump_device *msa0_dump_dev; bool is_wlan_mac_set; struct icnss_wlan_mac_addr wlan_mac_addr; bool bypass_s1_smmu; } *penv; static void icnss_pm_stay_awake(struct icnss_priv *priv) Loading Loading @@ -2914,6 +2915,7 @@ static int icnss_smmu_init(struct icnss_priv *priv) goto map_fail; } if (!priv->bypass_s1_smmu) { ret = iommu_domain_set_attr(mapping->domain, DOMAIN_ATTR_ATOMIC, &atomic_ctx); Loading @@ -2922,6 +2924,7 @@ static int icnss_smmu_init(struct icnss_priv *priv) ret); goto set_attr_fail; } } ret = iommu_domain_set_attr(mapping->domain, DOMAIN_ATTR_S1_BYPASS, Loading Loading @@ -3666,6 +3669,11 @@ static int icnss_probe(struct platform_device *pdev) if (ret == -EPROBE_DEFER) goto out; if (of_property_read_bool(pdev->dev.of_node, "qcom,smmu-s1-bypass")) priv->bypass_s1_smmu = true; icnss_pr_dbg("SMMU S1 BYPASS = %d\n", priv->bypass_s1_smmu); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase"); if (!res) { icnss_pr_err("Memory base not found in DT\n"); Loading Loading
Documentation/devicetree/bindings/cnss/icnss.txt +2 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,7 @@ Required properties: Optional properties: - qcom,icnss-vadc: VADC handle for vph_pwr read APIs. - qcom,icnss-adc_tm: VADC handle for vph_pwr notification APIs. - qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass Example: Loading @@ -43,4 +44,5 @@ Example: <0 140 0 /* CE10 */ >, <0 141 0 /* CE11 */ >; qcom,wlan-msa-memory = <0x200000>; qcom,smmu-s1-bypass; };
arch/arm/boot/dts/qcom/sdm630.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1458,6 +1458,7 @@ <0 424 0>, /* CE10 */ <0 425 0>; /* CE11 */ qcom,wlan-msa-memory = <0x100000>; qcom,smmu-s1-bypass; }; qcom,lpass@15700000 { Loading
arch/arm/boot/dts/qcom/sdm660.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -1891,6 +1891,7 @@ <0 424 0>, /* CE10 */ <0 425 0>; /* CE11 */ qcom,wlan-msa-memory = <0x100000>; qcom,smmu-s1-bypass; }; qcom,lpass@15700000 { Loading
drivers/soc/qcom/icnss.c +15 −7 Original line number Diff line number Diff line Loading @@ -334,6 +334,7 @@ static struct icnss_priv { struct ramdump_device *msa0_dump_dev; bool is_wlan_mac_set; struct icnss_wlan_mac_addr wlan_mac_addr; bool bypass_s1_smmu; } *penv; static void icnss_pm_stay_awake(struct icnss_priv *priv) Loading Loading @@ -2914,6 +2915,7 @@ static int icnss_smmu_init(struct icnss_priv *priv) goto map_fail; } if (!priv->bypass_s1_smmu) { ret = iommu_domain_set_attr(mapping->domain, DOMAIN_ATTR_ATOMIC, &atomic_ctx); Loading @@ -2922,6 +2924,7 @@ static int icnss_smmu_init(struct icnss_priv *priv) ret); goto set_attr_fail; } } ret = iommu_domain_set_attr(mapping->domain, DOMAIN_ATTR_S1_BYPASS, Loading Loading @@ -3666,6 +3669,11 @@ static int icnss_probe(struct platform_device *pdev) if (ret == -EPROBE_DEFER) goto out; if (of_property_read_bool(pdev->dev.of_node, "qcom,smmu-s1-bypass")) priv->bypass_s1_smmu = true; icnss_pr_dbg("SMMU S1 BYPASS = %d\n", priv->bypass_s1_smmu); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase"); if (!res) { icnss_pr_err("Memory base not found in DT\n"); Loading