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Commit 969473a9 authored by Hardik Kantilal Patel's avatar Hardik Kantilal Patel
Browse files

icnss: Avoid DOMAIN_ATTR_ATOMIC setting during S1 bypass 



While initializing the SMMU with DOMAIN_ATTR_ATOMIC attribute
iommu driver always vote for aggre2_noc_clk during suspend mode
which result into power penalty. To resolve this issue avoid
configuring DOMAIN_ATTR_ATOMIC attribute in S1_BYPASS mode.

CRs-fixed: 2004562
Change-Id: Ic5d4b2864f58098fd29da48e5f977434e356b1e0
Signed-off-by: default avatarHardik Kantilal Patel <hkpatel@codeaurora.org>
parent e44080d3

Documentation/devicetree/bindings/cnss/icnss.txt

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ Required properties: 
Optional properties:

  - qcom,icnss-vadc: VADC handle for vph_pwr read APIs.

  - qcom,icnss-adc_tm: VADC handle for vph_pwr notification APIs.

  - qcom,smmu-s1-bypass: Boolean context flag to set SMMU to S1 bypass



Example:
@@ -43,4 +44,5 @@ Example: 
		   <0 140 0 /* CE10 */ >,

		   <0 141 0 /* CE11 */ >;

        qcom,wlan-msa-memory = <0x200000>;

	qcom,smmu-s1-bypass;

    };

drivers/soc/qcom/icnss.c

+15 −7
Original line number Diff line number Diff line
@@ -334,6 +334,7 @@ static struct icnss_priv { 
	struct ramdump_device *msa0_dump_dev;

	bool is_wlan_mac_set;

	struct icnss_wlan_mac_addr wlan_mac_addr;

	bool bypass_s1_smmu;

} *penv;



static void icnss_pm_stay_awake(struct icnss_priv *priv)
@@ -2914,6 +2915,7 @@ static int icnss_smmu_init(struct icnss_priv *priv) 
		goto map_fail;

	}



	if (!priv->bypass_s1_smmu) {

		ret = iommu_domain_set_attr(mapping->domain,

					    DOMAIN_ATTR_ATOMIC,

					    &atomic_ctx);
@@ -2922,6 +2924,7 @@ static int icnss_smmu_init(struct icnss_priv *priv) 
				     ret);

			goto set_attr_fail;

		}

	}



	ret = iommu_domain_set_attr(mapping->domain,

				    DOMAIN_ATTR_S1_BYPASS,
@@ -3666,6 +3669,11 @@ static int icnss_probe(struct platform_device *pdev) 
	if (ret == -EPROBE_DEFER)

		goto out;



	if (of_property_read_bool(pdev->dev.of_node, "qcom,smmu-s1-bypass"))

		priv->bypass_s1_smmu = true;



	icnss_pr_dbg("SMMU S1 BYPASS = %d\n", priv->bypass_s1_smmu);



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase");

	if (!res) {

		icnss_pr_err("Memory base not found in DT\n");