Loading arch/arm/boot/dts/qcom/msmfalcon.dtsi +15 −0 Original line number Diff line number Diff line Loading @@ -839,6 +839,21 @@ }; }; arm64-cpu-erp { compatible = "arm,arm64-cpu-erp"; interrupts = <0 43 4>, <0 44 4>, <0 41 4>, <0 42 4>; interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq"; poll-delay-ms = <5000>; }; clock_rpmcc: qcom,rpmcc { compatible = "qcom,rpmcc-msmfalcon", "qcom,rpmcc"; #clock-cells = <1>; Loading Loading
arch/arm/boot/dts/qcom/msmfalcon.dtsi +15 −0 Original line number Diff line number Diff line Loading @@ -839,6 +839,21 @@ }; }; arm64-cpu-erp { compatible = "arm,arm64-cpu-erp"; interrupts = <0 43 4>, <0 44 4>, <0 41 4>, <0 42 4>; interrupt-names = "pri-dbe-irq", "sec-dbe-irq", "pri-ext-irq", "sec-ext-irq"; poll-delay-ms = <5000>; }; clock_rpmcc: qcom,rpmcc { compatible = "qcom,rpmcc-msmfalcon", "qcom,rpmcc"; #clock-cells = <1>; Loading