Merge "ARM: dts: msm: Add cpu cache nodes for msmtriton" (ca5c3769) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm/boot/dts/qcom/msmfalcon.dtsi

+163 −0

Original line number	Diff line number	Diff line
		@@ -49,6 +49,22 @@
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile0>;
		qcom,ea = <&ea0>;
		efficiency = <1024>;
		next-level-cache = <&L2_0>;
		L2_0: l2-cache {
		compatible = "arm,arch-cache";
		cache-level = <2>;
		/* A53 L2 dump not supported */
		qcom,dump-size = <0x0>;
		};
		L1_I_0: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_0: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU1: cpu@1 {
		@@ -58,6 +74,16 @@
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile0>;
		qcom,ea = <&ea1>;
		efficiency = <1024>;
		next-level-cache = <&L2_0>;
		L1_I_1: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_1: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU2: cpu@2 {
		@@ -67,6 +93,16 @@
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile0>;
		qcom,ea = <&ea2>;
		efficiency = <1024>;
		next-level-cache = <&L2_0>;
		L1_I_2: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_2: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU3: cpu@3 {
		@@ -76,6 +112,16 @@
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile0>;
		qcom,ea = <&ea3>;
		efficiency = <1024>;
		next-level-cache = <&L2_0>;
		L1_I_3: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_3: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU4: cpu@100 {
		@@ -85,6 +131,20 @@
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile1>;
		qcom,ea = <&ea4>;
		efficiency = <1536>;
		next-level-cache = <&L2_1>;
		L2_1: l2-cache {
		compatible = "arm,arch-cache";
		cache-level = <2>;
		};
		L1_I_100: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		L1_D_100: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		};

		CPU5: cpu@101 {
		@@ -94,6 +154,16 @@
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile2>;
		qcom,ea = <&ea5>;
		efficiency = <1536>;
		next-level-cache = <&L2_1>;
		L1_I_101: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		L1_D_101: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		};

		CPU6: cpu@102 {
		@@ -103,6 +173,16 @@
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile3>;
		qcom,ea = <&ea6>;
		efficiency = <1536>;
		next-level-cache = <&L2_1>;
		L1_I_102: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		L1_D_102: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		};

		CPU7: cpu@103 {
		@@ -112,6 +192,16 @@
		enable-method = "psci";
		qcom,limits-info = <&mitigation_profile4>;
		qcom,ea = <&ea7>;
		efficiency = <1536>;
		next-level-cache = <&L2_1>;
		L1_I_103: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		L1_D_103: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		};

		cpu-map {
		@@ -309,6 +399,74 @@
		status = "ok";
		};

		cpuss_dump {
		compatible = "qcom,cpuss-dump";
		qcom,l1_i_cache0 {
		qcom,dump-node = <&L1_I_0>;
		qcom,dump-id = <0x60>;
		};
		qcom,l1_i_cache1 {
		qcom,dump-node = <&L1_I_1>;
		qcom,dump-id = <0x61>;
		};
		qcom,l1_i_cache2 {
		qcom,dump-node = <&L1_I_2>;
		qcom,dump-id = <0x62>;
		};
		qcom,l1_i_cache3 {
		qcom,dump-node = <&L1_I_3>;
		qcom,dump-id = <0x63>;
		};
		qcom,l1_i_cache100 {
		qcom,dump-node = <&L1_I_100>;
		qcom,dump-id = <0x64>;
		};
		qcom,l1_i_cache101 {
		qcom,dump-node = <&L1_I_101>;
		qcom,dump-id = <0x65>;
		};
		qcom,l1_i_cache102 {
		qcom,dump-node = <&L1_I_102>;
		qcom,dump-id = <0x66>;
		};
		qcom,l1_i_cache103 {
		qcom,dump-node = <&L1_I_103>;
		qcom,dump-id = <0x67>;
		};
		qcom,l1_d_cache0 {
		qcom,dump-node = <&L1_D_0>;
		qcom,dump-id = <0x80>;
		};
		qcom,l1_d_cache1 {
		qcom,dump-node = <&L1_D_1>;
		qcom,dump-id = <0x81>;
		};
		qcom,l1_d_cache2 {
		qcom,dump-node = <&L1_D_2>;
		qcom,dump-id = <0x82>;
		};
		qcom,l1_d_cache3 {
		qcom,dump-node = <&L1_D_3>;
		qcom,dump-id = <0x83>;
		};
		qcom,l1_d_cache100 {
		qcom,dump-node = <&L1_D_100>;
		qcom,dump-id = <0x84>;
		};
		qcom,l1_d_cache101 {
		qcom,dump-node = <&L1_D_101>;
		qcom,dump-id = <0x85>;
		};
		qcom,l1_d_cache102 {
		qcom,dump-node = <&L1_D_102>;
		qcom,dump-id = <0x86>;
		};
		qcom,l1_d_cache103 {
		qcom,dump-node = <&L1_D_103>;
		qcom,dump-id = <0x87>;
		};
		};

		wdog: qcom,wdt@17817000 {
		status = "disabled";
		compatible = "qcom,msm-watchdog";
		@@ -1210,6 +1368,11 @@
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
		compatible = "qcom,msm-imem-mem_dump_table";
		reg = <0x10 8>;
		};

		dload_type@18 {
		compatible = "qcom,msm-imem-dload-type";
		reg = <0x18 4>;

arch/arm/boot/dts/qcom/msmtriton.dtsi

+165 −0

Original line number	Diff line number	Diff line
		@@ -46,6 +46,22 @@
		compatible = "arm,armv8";
		reg = <0x0 0x100>;
		enable-method = "psci";
		efficiency = <1024>;
		next-level-cache = <&L2_1>;
		L2_1: l2-cache {
		compatible = "arm,arch-cache";
		cache-level = <2>;
		/* A53 L2 dump not supported */
		qcom,dump-size = <0x0>;
		};
		L1_I_100: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_100: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU1: cpu@101 {
		@@ -53,6 +69,16 @@
		compatible = "arm,armv8";
		reg = <0x0 0x101>;
		enable-method = "psci";
		efficiency = <1024>;
		next-level-cache = <&L2_1>;
		L1_I_101: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_101: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU2: cpu@102 {
		@@ -60,6 +86,16 @@
		compatible = "arm,armv8";
		reg = <0x0 0x102>;
		enable-method = "psci";
		efficiency = <1024>;
		next-level-cache = <&L2_1>;
		L1_I_102: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_102: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU3: cpu@103 {
		@@ -67,6 +103,16 @@
		compatible = "arm,armv8";
		reg = <0x0 0x103>;
		enable-method = "psci";
		efficiency = <1024>;
		next-level-cache = <&L2_1>;
		L1_I_103: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_103: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU4: cpu@0 {
		@@ -74,6 +120,22 @@
		compatible = "arm,armv8";
		reg = <0x0 0x0>;
		enable-method = "psci";
		efficiency = <1024>;
		next-level-cache = <&L2_0>;
		L2_0: l2-cache {
		compatible = "arm,arch-cache";
		cache-level = <2>;
		/* A53 L2 dump not supported */
		qcom,dump-size = <0x0>;
		};
		L1_I_0: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_0: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU5: cpu@1 {
		@@ -81,6 +143,16 @@
		compatible = "arm,armv8";
		reg = <0x0 0x1>;
		enable-method = "psci";
		efficiency = <1024>;
		next-level-cache = <&L2_0>;
		L1_I_1: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_1: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU6: cpu@2 {
		@@ -88,6 +160,16 @@
		compatible = "arm,armv8";
		reg = <0x0 0x2>;
		enable-method = "psci";
		efficiency = <1024>;
		next-level-cache = <&L2_0>;
		L1_I_2: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_2: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU7: cpu@3 {
		@@ -95,6 +177,16 @@
		compatible = "arm,armv8";
		reg = <0x0 0x3>;
		enable-method = "psci";
		efficiency = <1024>;
		next-level-cache = <&L2_0>;
		L1_I_3: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_3: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		cpu-map {
		@@ -248,6 +340,74 @@
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
		};

		cpuss_dump {
		compatible = "qcom,cpuss-dump";
		qcom,l1_i_cache0 {
		qcom,dump-node = <&L1_I_0>;
		qcom,dump-id = <0x60>;
		};
		qcom,l1_i_cache1 {
		qcom,dump-node = <&L1_I_1>;
		qcom,dump-id = <0x61>;
		};
		qcom,l1_i_cache2 {
		qcom,dump-node = <&L1_I_2>;
		qcom,dump-id = <0x62>;
		};
		qcom,l1_i_cache3 {
		qcom,dump-node = <&L1_I_3>;
		qcom,dump-id = <0x63>;
		};
		qcom,l1_i_cache100 {
		qcom,dump-node = <&L1_I_100>;
		qcom,dump-id = <0x64>;
		};
		qcom,l1_i_cache101 {
		qcom,dump-node = <&L1_I_101>;
		qcom,dump-id = <0x65>;
		};
		qcom,l1_i_cache102 {
		qcom,dump-node = <&L1_I_102>;
		qcom,dump-id = <0x66>;
		};
		qcom,l1_i_cache103 {
		qcom,dump-node = <&L1_I_103>;
		qcom,dump-id = <0x67>;
		};
		qcom,l1_d_cache0 {
		qcom,dump-node = <&L1_D_0>;
		qcom,dump-id = <0x80>;
		};
		qcom,l1_d_cache1 {
		qcom,dump-node = <&L1_D_1>;
		qcom,dump-id = <0x81>;
		};
		qcom,l1_d_cache2 {
		qcom,dump-node = <&L1_D_2>;
		qcom,dump-id = <0x82>;
		};
		qcom,l1_d_cache3 {
		qcom,dump-node = <&L1_D_3>;
		qcom,dump-id = <0x83>;
		};
		qcom,l1_d_cache100 {
		qcom,dump-node = <&L1_D_100>;
		qcom,dump-id = <0x84>;
		};
		qcom,l1_d_cache101 {
		qcom,dump-node = <&L1_D_101>;
		qcom,dump-id = <0x85>;
		};
		qcom,l1_d_cache102 {
		qcom,dump-node = <&L1_D_102>;
		qcom,dump-id = <0x86>;
		};
		qcom,l1_d_cache103 {
		qcom,dump-node = <&L1_D_103>;
		qcom,dump-id = <0x87>;
		};
		};

		qcom,sps {
		compatible = "qcom,msm_sps_4k";
		qcom,pipe-attr-ee;
		@@ -736,6 +896,11 @@
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
		compatible = "qcom,msm-imem-mem_dump_table";
		reg = <0x10 8>;
		};

		dload_type@18 {
		compatible = "qcom,msm-imem-dload-type";
		reg = <0x18 4>;