Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f443c346 authored by Srinivas Ramana's avatar Srinivas Ramana
Browse files

ARM: dts: msm: Add cpu cache nodes for msmtriton 



Add cpu cache nodes to represent the cache hierarchy and
to specify the dump size of each cache.

While at it also add the cache dump nodes which will enable
reserving the memory for cache dumps.

Change-Id: I1d80ac853eb283c411985ceebd0dc31ed046836a
Signed-off-by: default avatarSrinivas Ramana <sramana@codeaurora.org>
parent c3f3cfdb

arch/arm/boot/dts/qcom/msmtriton.dtsi

+165 −0
Original line number Diff line number Diff line
@@ -46,6 +46,22 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_1>;

			L2_1: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <2>;

				/* A53 L2 dump not supported */

				qcom,dump-size = <0x0>;

			};

			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

		};



		CPU1: cpu@101 {
@@ -53,6 +69,16 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x101>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_1>;

			L1_I_101: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_101: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

		};



		CPU2: cpu@102 {
@@ -60,6 +86,16 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x102>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_1>;

			L1_I_102: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_102: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

		};



		CPU3: cpu@103 {
@@ -67,6 +103,16 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x103>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_1>;

			L1_I_103: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_103: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

		};



		CPU4: cpu@0 {
@@ -74,6 +120,22 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x0>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_0>;

			L2_0: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <2>;

				/* A53 L2 dump not supported */

				qcom,dump-size = <0x0>;

			};

			L1_I_0: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_0: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

		};



		CPU5: cpu@1 {
@@ -81,6 +143,16 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_0>;

			L1_I_1: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_1: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

		};



		CPU6: cpu@2 {
@@ -88,6 +160,16 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x2>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_0>;

			L1_I_2: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_2: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

		};



		CPU7: cpu@3 {
@@ -95,6 +177,16 @@ 
			compatible = "arm,armv8";

			reg = <0x0 0x3>;

			enable-method = "psci";

			efficiency = <1024>;

			next-level-cache = <&L2_0>;

			L1_I_3: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

			L1_D_3: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9040>;

			};

		};



		cpu-map {
@@ -248,6 +340,74 @@ 
		reg-names = "pshold-base", "tcsr-boot-misc-detect";

	};



	cpuss_dump {

		compatible = "qcom,cpuss-dump";

		qcom,l1_i_cache0 {

			qcom,dump-node = <&L1_I_0>;

			qcom,dump-id = <0x60>;

		};

		qcom,l1_i_cache1 {

			qcom,dump-node = <&L1_I_1>;

			qcom,dump-id = <0x61>;

		};

		qcom,l1_i_cache2 {

			qcom,dump-node = <&L1_I_2>;

			qcom,dump-id = <0x62>;

		};

		qcom,l1_i_cache3 {

			qcom,dump-node = <&L1_I_3>;

			qcom,dump-id = <0x63>;

		};

		qcom,l1_i_cache100 {

			qcom,dump-node = <&L1_I_100>;

			qcom,dump-id = <0x64>;

		};

		qcom,l1_i_cache101 {

			qcom,dump-node = <&L1_I_101>;

			qcom,dump-id = <0x65>;

		};

		qcom,l1_i_cache102 {

			qcom,dump-node = <&L1_I_102>;

			qcom,dump-id = <0x66>;

		};

		qcom,l1_i_cache103 {

			qcom,dump-node = <&L1_I_103>;

			qcom,dump-id = <0x67>;

		};

		qcom,l1_d_cache0 {

			qcom,dump-node = <&L1_D_0>;

			qcom,dump-id = <0x80>;

		};

		qcom,l1_d_cache1 {

			qcom,dump-node = <&L1_D_1>;

			qcom,dump-id = <0x81>;

		};

		qcom,l1_d_cache2 {

			qcom,dump-node = <&L1_D_2>;

			qcom,dump-id = <0x82>;

		};

		qcom,l1_d_cache3 {

			qcom,dump-node = <&L1_D_3>;

			qcom,dump-id = <0x83>;

		};

		qcom,l1_d_cache100 {

			qcom,dump-node = <&L1_D_100>;

			qcom,dump-id = <0x84>;

		};

		qcom,l1_d_cache101 {

			qcom,dump-node = <&L1_D_101>;

			qcom,dump-id = <0x85>;

		};

		qcom,l1_d_cache102 {

			qcom,dump-node = <&L1_D_102>;

			qcom,dump-id = <0x86>;

		};

		qcom,l1_d_cache103 {

			qcom,dump-node = <&L1_D_103>;

			qcom,dump-id = <0x87>;

		};

	};



	qcom,sps {

		compatible = "qcom,msm_sps_4k";

		qcom,pipe-attr-ee;
@@ -736,6 +896,11 @@ 
		#address-cells = <1>;

		#size-cells = <1>;



		mem_dump_table@10 {

			compatible = "qcom,msm-imem-mem_dump_table";

			reg = <0x10 8>;

		};



		dload_type@18 {

			compatible = "qcom,msm-imem-dload-type";

			reg = <0x18 4>;