Loading drivers/clk/qcom/mmcc-msmfalcon.c +4 −4 Original line number Diff line number Diff line Loading @@ -112,8 +112,8 @@ static const struct parent_map mmcc_parent_map_1[] = { static const char * const mmcc_parent_names_1[] = { "xo", "dsi0_phy_pll_out_byteclk", "dsi1_phy_pll_out_byteclk", "dsi0pll_byte_clk_mux", "dsi1pll_byte_clk_mux", "core_bi_pll_test_se", }; Loading Loading @@ -240,8 +240,8 @@ static const struct parent_map mmcc_parent_map_8[] = { static const char * const mmcc_parent_names_8[] = { "xo", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_dsiclk", "dsi0pll_pixel_clk_mux", "dsi1pll_pixel_clk_mux", "core_bi_pll_test_se", }; Loading Loading
drivers/clk/qcom/mmcc-msmfalcon.c +4 −4 Original line number Diff line number Diff line Loading @@ -112,8 +112,8 @@ static const struct parent_map mmcc_parent_map_1[] = { static const char * const mmcc_parent_names_1[] = { "xo", "dsi0_phy_pll_out_byteclk", "dsi1_phy_pll_out_byteclk", "dsi0pll_byte_clk_mux", "dsi1pll_byte_clk_mux", "core_bi_pll_test_se", }; Loading Loading @@ -240,8 +240,8 @@ static const struct parent_map mmcc_parent_map_8[] = { static const char * const mmcc_parent_names_8[] = { "xo", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_dsiclk", "dsi0pll_pixel_clk_mux", "dsi1pll_pixel_clk_mux", "core_bi_pll_test_se", }; Loading