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Commit bceea9fe authored by Loc Ho's avatar Loc Ho Committed by Greg Kroah-Hartman
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clk: xgene: Add missing parenthesis when clearing divider value 



commit 0f4c7a138dfefb0ebdbaf56e3ba2acd2958a6605 upstream.

In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.

Signed-off-by: default avatarLoc Ho <lho@apm.com>
Acked-by: default avatarToan Le <toanle@apm.com>
Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0d9529e1

drivers/clk/clk-xgene.c

+2 −2
Original line number Diff line number Diff line
@@ -351,8 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate, 
		/* Set new divider */

		data = xgene_clk_read(pclk->param.divider_reg +

				pclk->param.reg_divider_offset);

		data &= ~((1 << pclk->param.reg_divider_width) - 1)

				<< pclk->param.reg_divider_shift;

		data &= ~(((1 << pclk->param.reg_divider_width) - 1)

				<< pclk->param.reg_divider_shift);

		data |= divider;

		xgene_clk_write(data, pclk->param.divider_reg +

					pclk->param.reg_divider_offset);