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Commit bafa4fbc authored by Imre Deak's avatar Imre Deak Committed by Greg Kroah-Hartman
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drm/i915/bdw: Add missing delay during L3 SQC credit programming 



commit d6a862fe8c48229ba342648bcd535b2404724603 upstream.

BSpec requires us to wait ~100 clocks before re-enabling clock gating,
so make sure we do this.

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-2-git-send-email-imre.deak@intel.com


(cherry picked from commit 48e5d68d28f00c0cadac5a830980ff3222781abb)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent bf12e894

drivers/gpu/drm/i915/intel_pm.c

+6 −0
Original line number Diff line number Diff line
@@ -6620,6 +6620,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev) 
	misccpctl = I915_READ(GEN7_MISCCPCTL);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);

	I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);

	/*

	 * Wait at least 100 clocks before re-enabling clock gating. See

	 * the definition of L3SQCREG1 in BSpec.

	 */

	POSTING_READ(GEN8_L3SQCREG1);

	udelay(1);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl);



	/*