Loading arch/arm64/mm/context.c +3 −2 Original line number Diff line number Diff line Loading @@ -191,6 +191,9 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); switch_mm_fastpath: arm64_apply_bp_hardening(); /* * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when * emulating PAN. Loading @@ -206,8 +209,6 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); arm64_apply_bp_hardening(); } static int asids_init(void) Loading Loading
arch/arm64/mm/context.c +3 −2 Original line number Diff line number Diff line Loading @@ -191,6 +191,9 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); switch_mm_fastpath: arm64_apply_bp_hardening(); /* * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when * emulating PAN. Loading @@ -206,8 +209,6 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); arm64_apply_bp_hardening(); } static int asids_init(void) Loading