Merge "arm64: Add BTAC/LinkStack sanitizations for Kryo cores" (fe3ef6b4) · Commits · e / devices / android_kernel_sony_msm8998

arch/arm64/include/asm/cputype.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -86,6 +86,7 @@
		#define ARM_CPU_PART_CORTEX_A75 0xD0A
		#define ARM_CPU_PART_KRYO2XX_GOLD 0x800
		#define ARM_CPU_PART_KRYO2XX_SILVER 0x801
		#define QCOM_CPU_PART_KRYO 0x200

		#define APM_CPU_PART_POTENZA 0x000

		@@ -101,6 +102,7 @@
		MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER)
		#define MIDR_KRYO2XX_GOLD \
		MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD)
		#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

		#ifndef __ASSEMBLY__

arch/arm64/kernel/cpu_errata.c

+31 −5

Original line number	Diff line number	Diff line
		@@ -29,6 +29,18 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry)
		entry->midr_range_max);
		}

		static bool __maybe_unused
		is_kryo_midr(const struct arm64_cpu_capabilities *entry)
		{
		u32 model;

		model = read_cpuid_id();
		model &= MIDR_IMPLEMENTOR_MASK \| (0xf00 << MIDR_PARTNUM_SHIFT) \|
		MIDR_ARCHITECTURE_MASK;

		return model == entry->midr_model;
		}

		#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
		#include <asm/mmu_context.h>
		#include <asm/cacheflush.h>
		@@ -139,16 +151,24 @@ static void __maybe_unused qcom_link_stack_sanitization(void)
		: "=&r" (tmp));
		}

		static int __maybe_unused qcom_enable_link_stack_sanitization(void *data)
		static void __maybe_unused qcom_bp_hardening(void)
		{
		const struct arm64_cpu_capabilities *entry = data;
		qcom_link_stack_sanitization();
		if (psci_ops.get_version)
		psci_ops.get_version();
		}

		install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
		__qcom_hyp_sanitize_link_stack_start,
		__qcom_hyp_sanitize_link_stack_end);
		static int __maybe_unused enable_qcom_bp_hardening(void *data)
		{
		const struct arm64_cpu_capabilities *entry = data;

		install_bp_hardening_cb(entry,
		(bp_hardening_cb_t)qcom_bp_hardening,
		__psci_hyp_bp_inval_start,
		__psci_hyp_bp_inval_end);
		return 0;
		}

		#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */

		#define MIDR_RANGE(model, min, max) \
		@@ -257,6 +277,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
		MIDR_ALL_VERSIONS(MIDR_KRYO2XX_GOLD),
		.enable = enable_psci_bp_hardening,
		},
		{
		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
		.midr_model = MIDR_QCOM_KRYO,
		.matches = is_kryo_midr,
		.enable = enable_qcom_bp_hardening,
		},
		#endif
		{
		}