Loading Documentation/hwmon/ina2xx +1 −1 Original line number Diff line number Diff line Loading @@ -32,7 +32,7 @@ Supported chips: Datasheet: Publicly available at the Texas Instruments website http://www.ti.com/ Author: Lothar Felten <l-felten@ti.com> Author: Lothar Felten <lothar.felten@gmail.com> Description ----------- Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 4 SUBLEVEL = 159 SUBLEVEL = 160 EXTRAVERSION = NAME = Blurry Fish Butt Loading arch/arm/boot/dts/dra7.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -1549,7 +1549,7 @@ }; }; dcan1: can@481cc000 { dcan1: can@4ae3c000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan1"; reg = <0x4ae3c000 0x2000>; Loading @@ -1559,7 +1559,7 @@ status = "disabled"; }; dcan2: can@481d0000 { dcan2: can@48480000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan2"; reg = <0x48480000 0x2000>; Loading arch/arm/mach-mvebu/pmsu.c +3 −3 Original line number Diff line number Diff line Loading @@ -117,8 +117,8 @@ void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); } extern unsigned char mvebu_boot_wa_start; extern unsigned char mvebu_boot_wa_end; extern unsigned char mvebu_boot_wa_start[]; extern unsigned char mvebu_boot_wa_end[]; /* * This function sets up the boot address workaround needed for SMP Loading @@ -131,7 +131,7 @@ int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target, phys_addr_t resume_addr_reg) { void __iomem *sram_virt_base; u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start; u32 code_len = mvebu_boot_wa_end - mvebu_boot_wa_start; mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE); mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute, Loading arch/arm64/include/asm/cpufeature.h +7 −1 Original line number Diff line number Diff line Loading @@ -38,7 +38,8 @@ #define ARM64_HAS_VIRT_HOST_EXTN 12 #define ARM64_HARDEN_BRANCH_PREDICTOR 13 #define ARM64_UNMAP_KERNEL_AT_EL0 14 #define ARM64_NCAPS 15 #define ARM64_HAS_32BIT_EL0 15 #define ARM64_NCAPS 16 #ifndef __ASSEMBLY__ Loading Loading @@ -190,6 +191,11 @@ static inline bool cpu_supports_mixed_endian_el0(void) return id_aa64mmfr0_mixed_endian_el0(read_cpuid(SYS_ID_AA64MMFR0_EL1)); } static inline bool system_supports_32bit_el0(void) { return cpus_have_cap(ARM64_HAS_32BIT_EL0); } static inline bool system_supports_mixed_endian_el0(void) { return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1)); Loading Loading
Documentation/hwmon/ina2xx +1 −1 Original line number Diff line number Diff line Loading @@ -32,7 +32,7 @@ Supported chips: Datasheet: Publicly available at the Texas Instruments website http://www.ti.com/ Author: Lothar Felten <l-felten@ti.com> Author: Lothar Felten <lothar.felten@gmail.com> Description ----------- Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 4 SUBLEVEL = 159 SUBLEVEL = 160 EXTRAVERSION = NAME = Blurry Fish Butt Loading
arch/arm/boot/dts/dra7.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -1549,7 +1549,7 @@ }; }; dcan1: can@481cc000 { dcan1: can@4ae3c000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan1"; reg = <0x4ae3c000 0x2000>; Loading @@ -1559,7 +1559,7 @@ status = "disabled"; }; dcan2: can@481d0000 { dcan2: can@48480000 { compatible = "ti,dra7-d_can"; ti,hwmods = "dcan2"; reg = <0x48480000 0x2000>; Loading
arch/arm/mach-mvebu/pmsu.c +3 −3 Original line number Diff line number Diff line Loading @@ -117,8 +117,8 @@ void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); } extern unsigned char mvebu_boot_wa_start; extern unsigned char mvebu_boot_wa_end; extern unsigned char mvebu_boot_wa_start[]; extern unsigned char mvebu_boot_wa_end[]; /* * This function sets up the boot address workaround needed for SMP Loading @@ -131,7 +131,7 @@ int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target, phys_addr_t resume_addr_reg) { void __iomem *sram_virt_base; u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start; u32 code_len = mvebu_boot_wa_end - mvebu_boot_wa_start; mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE); mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute, Loading
arch/arm64/include/asm/cpufeature.h +7 −1 Original line number Diff line number Diff line Loading @@ -38,7 +38,8 @@ #define ARM64_HAS_VIRT_HOST_EXTN 12 #define ARM64_HARDEN_BRANCH_PREDICTOR 13 #define ARM64_UNMAP_KERNEL_AT_EL0 14 #define ARM64_NCAPS 15 #define ARM64_HAS_32BIT_EL0 15 #define ARM64_NCAPS 16 #ifndef __ASSEMBLY__ Loading Loading @@ -190,6 +191,11 @@ static inline bool cpu_supports_mixed_endian_el0(void) return id_aa64mmfr0_mixed_endian_el0(read_cpuid(SYS_ID_AA64MMFR0_EL1)); } static inline bool system_supports_32bit_el0(void) { return cpus_have_cap(ARM64_HAS_32BIT_EL0); } static inline bool system_supports_mixed_endian_el0(void) { return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1)); Loading