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Commit a62fad39 authored by Ajay Singh Parmar's avatar Ajay Singh Parmar Committed by Kyle Yan
Browse files

clk: msm: hdmi: add cobalt hdmi pll calculator and clocks 



Add PLL and PHY programming for HDMI. Dynamically calculate
the register values to be programmed for a given pixel clock.

CRs-Fixed: 1022772
Change-Id: Ibf7877eb6edd29baefee57bc12188989d897d47e
Signed-off-by: default avatarAjay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: default avatarTatenda Chipeperekwa <tatendac@codeaurora.org>
parent 464c4377

Documentation/devicetree/bindings/fb/mdss-pll.txt

+2 −1
Original line number Diff line number Diff line
@@ -14,7 +14,8 @@ Required properties: 
			"qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",

			"qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",

			"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",

			"qcom,mdss_dsi_pll_cobalt", "qcom,mdss_dp_pll_cobalt"

			"qcom,mdss_dsi_pll_cobalt", "qcom,mdss_dp_pll_cobalt",

			"qcom,mdss_hdmi_pll_cobalt"

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

drivers/clk/msm/mdss/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -6,3 +6,4 @@ obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-cobalt.o 
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dp-pll-cobalt.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dp-pll-cobalt-util.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o

obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-cobalt.o

drivers/clk/msm/mdss/mdss-hdmi-pll-cobalt.c

0 → 100644
+841 −0

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drivers/clk/msm/mdss/mdss-hdmi-pll.h

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Original line number Diff line number Diff line 
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -33,6 +33,11 @@ struct hdmi_pll_vco_clk { 
	struct clk	c;

};



static inline struct hdmi_pll_vco_clk *to_hdmi_vco_clk(struct clk *clk)

{

	return container_of(clk, struct hdmi_pll_vco_clk, c);

}



int hdmi_pll_clock_register(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res);
@@ -50,4 +55,7 @@ int hdmi_8996_v3_pll_clock_register(struct platform_device *pdev, 


int hdmi_8996_v3_1p8_pll_clock_register(struct platform_device *pdev,

				 struct mdss_pll_resources *pll_res);



int hdmi_cobalt_pll_clock_register(struct platform_device *pdev,

				   struct mdss_pll_resources *pll_res);

#endif

drivers/clk/msm/mdss/mdss-pll.c

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