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Commit a580516d authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: s/dpio_lock/sb_lock/ 



Rename dpio_lock to sb_lock to inform the reader that its primary
purpose is to protect the sideband mailbox rather than some DPIO
state.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b12ce1d8

drivers/gpu/drm/i915/i915_dma.c

+1 −1
Original line number Diff line number Diff line
@@ -814,7 +814,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	spin_lock_init(&dev_priv->uncore.lock);

	spin_lock_init(&dev_priv->mm.object_stat_lock);

	spin_lock_init(&dev_priv->mmio_flip_lock);

	mutex_init(&dev_priv->dpio_lock);

	mutex_init(&dev_priv->sb_lock);

	mutex_init(&dev_priv->modeset_restore_lock);

	mutex_init(&dev_priv->csr_lock);

drivers/gpu/drm/i915/i915_drv.h

+2 −2
Original line number Diff line number Diff line
@@ -1666,8 +1666,8 @@ struct drm_i915_private { 
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */

	struct pm_qos_request pm_qos;



	/* DPIO indirect register protection */

	struct mutex dpio_lock;

	/* Sideband mailbox protection */

	struct mutex sb_lock;



	/** Cached value of IMR to avoid reads in updating the bitfield */

	union {

drivers/gpu/drm/i915/intel_display.c

+28 −28
Original line number Diff line number Diff line
@@ -1140,9 +1140,9 @@ static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) 
	u32 val;

	bool cur_state;



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);

	val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	cur_state = val & DSI_PLL_VCO_EN;

	I915_STATE_WARN(cur_state != state,
@@ -1661,7 +1661,7 @@ static void chv_enable_pll(struct intel_crtc *crtc, 


	BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	/* Enable back the 10bit clock to display controller */

	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
@@ -1684,7 +1684,7 @@ static void chv_enable_pll(struct intel_crtc *crtc, 
	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);

	POSTING_READ(DPLL_MD(pipe));



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



static int intel_num_dvo_pipes(struct drm_device *dev)
@@ -1826,7 +1826,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 
	I915_WRITE(DPLL(pipe), val);

	POSTING_READ(DPLL(pipe));



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	/* Disable 10bit clock to display controller */

	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
@@ -1844,7 +1844,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

	}



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
@@ -3939,7 +3939,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc) 
	u32 divsel, phaseinc, auxdiv, phasedir = 0;

	u32 temp;



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	/* It is necessary to ungate the pixclk gate prior to programming

	 * the divisors, and gate it back when it is done.
@@ -4016,7 +4016,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc) 


	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
@@ -5728,10 +5728,10 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv) 
	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };



	/* Obtain SKU information */

	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);

	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &

		CCK_FUSE_HPLL_FREQ_MASK;

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	return vco_freq[hpll_freq] * 1000;

}
@@ -5785,7 +5785,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) 


		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;



		mutex_lock(&dev_priv->dpio_lock);

		mutex_lock(&dev_priv->sb_lock);

		/* adjust cdclk divider */

		val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);

		val &= ~DISPLAY_FREQUENCY_VALUES;
@@ -5796,10 +5796,10 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) 
			      DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),

			     50))

			DRM_ERROR("timed out waiting for CDclk change\n");

		mutex_unlock(&dev_priv->dpio_lock);

		mutex_unlock(&dev_priv->sb_lock);

	}



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);

	/* adjust self-refresh exit latency value */

	val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);

	val &= ~0x7f;
@@ -5813,7 +5813,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) 
	else

		val |= 3000 / 250; /* 3.0 usec */

	vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	vlv_update_cdclk(dev);

}
@@ -6741,9 +6741,9 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev) 
	if (dev_priv->hpll_freq == 0)

		dev_priv->hpll_freq = valleyview_get_vco(dev_priv);



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);

	val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	divider = val & DISPLAY_FREQUENCY_VALUES;
@@ -7085,7 +7085,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, 
	u32 bestn, bestm1, bestm2, bestp1, bestp2;

	u32 coreclk, reg_val;



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	bestn = pipe_config->dpll.n;

	bestm1 = pipe_config->dpll.m1;
@@ -7163,7 +7163,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, 
	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);



	vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



static void chv_update_pll(struct intel_crtc *crtc,
@@ -7208,7 +7208,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, 
	I915_WRITE(dpll_reg,

		   pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	/* p1 and p2 divider */

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
@@ -7281,7 +7281,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, 
			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |

			DPIO_AFC_RECAL);



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



/**
@@ -7782,9 +7782,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, 
	if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))

		return;



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);

	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;

	clock.m2 = mdiv & DPIO_M2DIV_MASK;
@@ -7878,12 +7878,12 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, 
	u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;

	int refclk = 100000;



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);

	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));

	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));

	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));

	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;

	clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
@@ -8249,7 +8249,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, 
		 with_fdi, "LP PCH doesn't have FDI\n"))

		with_fdi = false;



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);

	tmp &= ~SBI_SSCCTL_DISABLE;
@@ -8275,7 +8275,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, 
	tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;

	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



/* Sequence to disable CLKOUT_DP */
@@ -8284,7 +8284,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t reg, tmp;



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?

	       SBI_GEN0 : SBI_DBUFF0;
@@ -8303,7 +8303,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev) 
		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);

	}



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



static void lpt_init_pch_refclk(struct drm_device *dev)

drivers/gpu/drm/i915/intel_dp.c

+14 −14
Original line number Diff line number Diff line
@@ -2355,7 +2355,7 @@ static void chv_post_disable_dp(struct intel_encoder *encoder) 


	intel_dp_link_down(intel_dp);



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	/* Propagate soft reset to data lane reset */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
@@ -2374,7 +2374,7 @@ static void chv_post_disable_dp(struct intel_encoder *encoder) 
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



static void
@@ -2671,7 +2671,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder) 
	int pipe = intel_crtc->pipe;

	u32 val;



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));

	val = 0;
@@ -2684,7 +2684,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder) 
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	intel_enable_dp(encoder);

}
@@ -2702,7 +2702,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 
	intel_dp_prepare(encoder);



	/* Program Tx lane resets to default */

	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),

			 DPIO_PCS_TX_LANE2_RESET |

			 DPIO_PCS_TX_LANE1_RESET);
@@ -2716,7 +2716,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



static void chv_pre_enable_dp(struct intel_encoder *encoder)
@@ -2732,7 +2732,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) 
	int data, i, stagger;

	u32 val;



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	/* allow hardware to manage TX FIFO reset source */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
@@ -2802,7 +2802,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) 
		       DPIO_TX1_STAGGER_MULT(7) |

		       DPIO_TX2_STAGGER_MULT(5));



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	intel_enable_dp(encoder);

}
@@ -2820,7 +2820,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 


	intel_dp_prepare(encoder);



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	/* program left/right clock distribution */

	if (pipe != PIPE_B) {
@@ -2870,7 +2870,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 
		val |= CHV_CMN_USEDCLKCHANNEL;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



/*
@@ -3095,7 +3095,7 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) 
		return 0;

	}



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
@@ -3104,7 +3104,7 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) 
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	return 0;

}
@@ -3191,7 +3191,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) 
		return 0;

	}



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	/* Clear calc init */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
@@ -3278,7 +3278,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) 
	val |= DPIO_LRC_BYPASS;

	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	return 0;

}

drivers/gpu/drm/i915/intel_dsi.c

+4 −4
Original line number Diff line number Diff line
@@ -239,7 +239,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, 


static void band_gap_reset(struct drm_i915_private *dev_priv)

{

	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);



	vlv_flisdsi_write(dev_priv, 0x08, 0x0001);

	vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
@@ -248,7 +248,7 @@ static void band_gap_reset(struct drm_i915_private *dev_priv) 
	vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);

	vlv_flisdsi_write(dev_priv, 0x08, 0x0000);



	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);

}



static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
@@ -346,11 +346,11 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) 


	DRM_DEBUG_KMS("\n");



	mutex_lock(&dev_priv->dpio_lock);

	mutex_lock(&dev_priv->sb_lock);

	/* program rcomp for compliance, reduce from 50 ohms to 45 ohms

	 * needed everytime after power gate */

	vlv_flisdsi_write(dev_priv, 0x04, 0x0004);

	mutex_unlock(&dev_priv->dpio_lock);

	mutex_unlock(&dev_priv->sb_lock);



	/* bandgap reset is needed after everytime we do power gate */

	band_gap_reset(dev_priv);