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Commit b12ce1d8 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Kill intel_flush_primary_plane() 



The primary plane frobbing was removed from the sprite code in
 commit ecce87ea
 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
 Date:   Tue Apr 21 17:12:50 2015 +0300

    drm/i915: Remove implicitly disabling primary plane for now

but the intel_flush_primary_plane() calls were left behind. Replace them
with straight forward POSTING_READ() of the sprite surface address
register.

The other user of intel_flush_primary_plane() is g4x_disable_trickle_feed()
where we can just inline the steps directly.

This allows intel_flush_primary_plane() to be killed off.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent fde61e4b

drivers/gpu/drm/i915/intel_display.c

+0 −14
Original line number Diff line number Diff line
@@ -2210,20 +2210,6 @@ static void intel_disable_pipe(struct intel_crtc *crtc) 
		intel_wait_for_pipe_off(crtc);

}



/*

 * Plane regs are double buffered, going from enabled->disabled needs a

 * trigger in order to latch.  The display address reg provides this.

 */

void intel_flush_primary_plane(struct drm_i915_private *dev_priv,

			       enum plane plane)

{

	struct drm_device *dev = dev_priv->dev;

	u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);



	I915_WRITE(reg, I915_READ(reg));

	POSTING_READ(reg);

}



/**

 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe

 * @plane:  plane to be enabled

drivers/gpu/drm/i915/intel_drv.h

+0 −2
Original line number Diff line number Diff line
@@ -1383,8 +1383,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); 


/* intel_sprite.c */

int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);

void intel_flush_primary_plane(struct drm_i915_private *dev_priv,

			       enum plane plane);

int intel_plane_restore(struct drm_plane *plane);

int intel_sprite_set_colorkey(struct drm_device *dev, void *data,

			      struct drm_file *file_priv);

drivers/gpu/drm/i915/intel_pm.c

+4 −2
Original line number Diff line number Diff line
@@ -5886,13 +5886,15 @@ static void ibx_init_clock_gating(struct drm_device *dev) 
static void g4x_disable_trickle_feed(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;

	enum pipe pipe;



	for_each_pipe(dev_priv, pipe) {

		I915_WRITE(DSPCNTR(pipe),

			   I915_READ(DSPCNTR(pipe)) |

			   DISPPLANE_TRICKLE_FEED_DISABLE);

		intel_flush_primary_plane(dev_priv, pipe);



		I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));

		POSTING_READ(DSPSURF(pipe));

	}

}

drivers/gpu/drm/i915/intel_sprite.c

+7 −23
Original line number Diff line number Diff line
@@ -282,7 +282,6 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force) 


	I915_WRITE(PLANE_CTL(pipe, plane), 0);



	/* Activate double buffered register update */

	I915_WRITE(PLANE_SURF(pipe, plane), 0);

	POSTING_READ(PLANE_SURF(pipe, plane));
@@ -339,7 +338,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, 
	struct drm_device *dev = dplane->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_plane *intel_plane = to_intel_plane(dplane);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct drm_i915_gem_object *obj = intel_fb_obj(fb);

	int pipe = intel_plane->pipe;

	int plane = intel_plane->plane;
@@ -453,8 +451,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, 
	I915_WRITE(SPCNTR(pipe, plane), sprctl);

	I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +

		   sprsurf_offset);



	intel_flush_primary_plane(dev_priv, intel_crtc->plane);

	POSTING_READ(SPSURF(pipe, plane));

}



static void
@@ -463,21 +460,17 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force) 
	struct drm_device *dev = dplane->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_plane *intel_plane = to_intel_plane(dplane);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_plane->pipe;

	int plane = intel_plane->plane;



	I915_WRITE(SPCNTR(pipe, plane), 0);



	/* Activate double buffered register update */

	I915_WRITE(SPSURF(pipe, plane), 0);



	intel_flush_primary_plane(dev_priv, intel_crtc->plane);

	POSTING_READ(SPSURF(pipe, plane));



	intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);

}





static void

ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,

		 struct drm_framebuffer *fb,
@@ -489,7 +482,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	struct drm_device *dev = plane->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_plane *intel_plane = to_intel_plane(plane);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct drm_i915_gem_object *obj = intel_fb_obj(fb);

	enum pipe pipe = intel_plane->pipe;

	u32 sprctl, sprscale = 0;
@@ -599,8 +591,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	I915_WRITE(SPRCTL(pipe), sprctl);

	I915_WRITE(SPRSURF(pipe),

		   i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);



	intel_flush_primary_plane(dev_priv, intel_crtc->plane);

	POSTING_READ(SPRSURF(pipe));

}



static void
@@ -609,17 +600,15 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force) 
	struct drm_device *dev = plane->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_plane *intel_plane = to_intel_plane(plane);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_plane->pipe;



	I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);

	/* Can't leave the scaler enabled... */

	if (intel_plane->can_scale)

		I915_WRITE(SPRSCALE(pipe), 0);

	/* Activate double buffered register update */

	I915_WRITE(SPRSURF(pipe), 0);



	intel_flush_primary_plane(dev_priv, intel_crtc->plane);

	I915_WRITE(SPRSURF(pipe), 0);

	POSTING_READ(SPRSURF(pipe));

}



static void
@@ -633,7 +622,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	struct drm_device *dev = plane->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_plane *intel_plane = to_intel_plane(plane);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	struct drm_i915_gem_object *obj = intel_fb_obj(fb);

	int pipe = intel_plane->pipe;

	unsigned long dvssurf_offset, linear_offset;
@@ -730,8 +718,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	I915_WRITE(DVSCNTR(pipe), dvscntr);

	I915_WRITE(DVSSURF(pipe),

		   i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);



	intel_flush_primary_plane(dev_priv, intel_crtc->plane);

	POSTING_READ(DVSSURF(pipe));

}



static void
@@ -740,17 +727,14 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force) 
	struct drm_device *dev = plane->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_plane *intel_plane = to_intel_plane(plane);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_plane->pipe;



	I915_WRITE(DVSCNTR(pipe), 0);

	/* Disable the scaler */

	I915_WRITE(DVSSCALE(pipe), 0);



	/* Flush double buffered register updates */

	I915_WRITE(DVSSURF(pipe), 0);



	intel_flush_primary_plane(dev_priv, intel_crtc->plane);

	POSTING_READ(DVSSURF(pipe));

}



static int