ARM: dts: msm: Update SDCC bus voting for SDM660

SDM660 target has a dual DDR channel of width 16 bits.
Update DDR bus bandwidth voting considering per channel
voting and update CNOC bus voting to support LOW_SVS
(i.e freq 33.33 MHz) considering bus width of 4 bytes.

Change-Id: Iff0a40016f58c82d0823fd0c1968f1af6978f68c
Signed-off-by: Sayali Lokhande <sayalil@codeaurora.org>