clk: msm: mdss: fix DSI PLL post vco divider configuration

The post vco divider clock in the DSI PLL can only be configured
to a fixed value of 1 or 4. Current implementation can result in
the divider being set to any value between 1 and 4 which can
result in failures while enabling the DSI pixel clock. Fix this
by replacing the post vco divider with a fixed /1 and /4 dividers
followed by a mux clock.

CRs-Fixed: 1064277
Change-Id: I01bc7304e446c622849c678c64a3fd6881413e89
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>