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Commit 959d8825 authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: msm: Add support for block reset clocks 



Add the block reset clocks which will be used by clients to
assert/deassert these clocks using the reset controller framework.

Change-Id: I3e9f7f85bf1faf0e1bb501196ba9d7e197111a03
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 4627274b

arch/arm/boot/dts/qcom/msm8996.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -781,6 +781,7 @@ 
		reg-names = "cc_base";

		vdd_dig-supply = <&pm8994_s1_corner>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_mmss: qcom,mmsscc@8c0000 {

drivers/clk/msm/clock-gcc-8996.c

+26 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -31,6 +31,7 @@ 
#include <dt-bindings/clock/msm-clocks-8996.h>

#include <dt-bindings/clock/msm-clocks-hwio-8996.h>



#include "reset.h"

#include "vdd-level-8996.h"



static void __iomem *virt_base;
@@ -3142,6 +3143,26 @@ static struct branch_clk gcc_aggre0_noc_mpu_cfg_ahb_clk = { 
	},

};



static const struct msm_reset_map gcc_msm8996_resets[] = {

	[QUSB2PHY_PRIM_BCR] = { 0x12038 },

	[QUSB2PHY_SEC_BCR] = { 0x1203c },

	[BLSP1_BCR] = { 0x17000 },

	[BLSP2_BCR] = { 0x25000 },

	[BOOT_ROM_BCR] = { 0x38000 },

	[PRNG_BCR] = { 0x34000 },

	[UFS_BCR] = { 0x75000 },

	[USB_20_BCR] = { 0x12000 },

	[USB_30_BCR] = { 0x0f000 },

	[USB3_PHY_BCR] = { 0x50020 },

	[USB3PHY_PHY_BCR] = { 0x50024 },

	[PCIE_0_PHY_BCR] = { 0x6c01c },

	[PCIE_1_PHY_BCR] = { 0x6d038 },

	[PCIE_2_PHY_BCR] = { 0x6e038 },

	[PCIE_PHY_BCR] = { 0x6f000 },

	[PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00C },

	[PCIE_PHY_COM_BCR] = { 0x6f014 },

};



static struct mux_clk gcc_debug_mux;

static struct mux_clk gcc_debug_mux_v2;

static struct clk_ops clk_ops_debug_mux;
@@ -3711,6 +3732,10 @@ static int msm_gcc_8996_probe(struct platform_device *pdev) 
	 */

	clk_set_flags(&gcc_mmss_bimc_gfx_clk.c, CLKFLAG_RETAIN_MEM);



	/* Register block resets */

	msm_reset_controller_register(pdev, gcc_msm8996_resets,

			ARRAY_SIZE(gcc_msm8996_resets), virt_base);



	dev_info(&pdev->dev, "Registered GCC clocks.\n");

	return 0;

}

drivers/clk/msm/clock-mmss-8996.c

+17 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 


#include "vdd-level-8996.h"

#include "clock.h"

#include "reset.h"



static void __iomem *virt_base;

static void __iomem *virt_base_gpu;
@@ -3032,6 +3033,17 @@ static struct branch_clk vmem_maxi_clk = { 
	},

};



static const struct msm_reset_map mmss_msm8996_resets[] = {

	[VIDEO_BCR] = { 0x1020 },

	[MDSS_BCR] = { 0x2300 },

	[CAMSS_MICRO_BCR] = { 0x3490 },

	[CAMSS_JPEG_BCR] = { 0x35a0 },

	[CAMSS_VFE0_BCR] = { 0x3660 },

	[CAMSS_VFE1_BCR] = { 0x3670 },

	[FD_BCR] = { 0x3b60 },

	[GPU_GX_BCR] = { 0x4020 },

};



static struct mux_clk mmss_gcc_dbg_clk = {

	.ops = &mux_reg_ops,

	.en_mask = BIT(16),
@@ -3778,6 +3790,11 @@ int msm_mmsscc_8996_probe(struct platform_device *pdev) 
		if (rc)

			return rc;

	}



	 /* Register block resets */

	msm_reset_controller_register(pdev, mmss_msm8996_resets,

			ARRAY_SIZE(mmss_msm8996_resets), virt_base);



	dev_info(&pdev->dev, "Registered MMSS clocks.\n");



	return platform_driver_register(&msm_clock_gpu_driver);

include/dt-bindings/clock/msm-clocks-8996.h

+29 −0
Original line number Diff line number Diff line
@@ -540,4 +540,33 @@ 
#define clk_sys_apcsaux_clk 0x0b0dd513

#define clk_cpu_debug_mux 0xc7acaa31



/* GCC block resets */

#define QUSB2PHY_PRIM_BCR		0

#define QUSB2PHY_SEC_BCR		1

#define BLSP1_BCR			2

#define BLSP2_BCR			3

#define BOOT_ROM_BCR			4

#define PRNG_BCR			5

#define UFS_BCR				6

#define USB_20_BCR			7

#define USB_30_BCR			8

#define USB3_PHY_BCR			9

#define USB3PHY_PHY_BCR			10

#define PCIE_0_PHY_BCR			11

#define PCIE_1_PHY_BCR			12

#define PCIE_2_PHY_BCR			13

#define PCIE_PHY_BCR			14

#define PCIE_PHY_COM_BCR		15

#define PCIE_PHY_NOCSR_COM_PHY_BCR	16



/* MMSS Block resets */

#define VIDEO_BCR			0

#define MDSS_BCR			1

#define CAMSS_MICRO_BCR			2

#define CAMSS_JPEG_BCR			3

#define CAMSS_VFE0_BCR			4

#define CAMSS_VFE1_BCR			5

#define FD_BCR				6

#define GPU_GX_BCR			7



#endif