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Commit 827d0483 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: msm: Add support for SMD-RPM clocks"

parents 1ece543f a4cd7d61

arch/arm/configs/msmfalcon_defconfig

+1 −1
Original line number Diff line number Diff line
@@ -420,7 +420,7 @@ CONFIG_IPA3=y 
CONFIG_RMNET_IPA3=y

CONFIG_GPIO_USB_DETECT=y

CONFIG_USB_BAM=y

CONFIG_MSM_MDSS_PLL=y

CONFIG_QCOM_CLK_SMD_RPM=y

CONFIG_REMOTE_SPINLOCK_MSM=y

CONFIG_ARM_SMMU=y

CONFIG_IOMMU_DEBUG=y

arch/arm64/configs/msmfalcon-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -473,6 +473,7 @@ CONFIG_RMNET_IPA3=y 
CONFIG_GPIO_USB_DETECT=y

CONFIG_SEEMP_CORE=y

CONFIG_USB_BAM=y

CONFIG_QCOM_CLK_SMD_RPM=y

CONFIG_REMOTE_SPINLOCK_MSM=y

CONFIG_IOMMU_IO_PGTABLE_FAST=y

CONFIG_ARM_SMMU=y

arch/arm64/configs/msmfalcon_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -483,6 +483,7 @@ CONFIG_RMNET_IPA3=y 
CONFIG_GPIO_USB_DETECT=y

CONFIG_SEEMP_CORE=y

CONFIG_USB_BAM=y

CONFIG_QCOM_CLK_SMD_RPM=y

CONFIG_REMOTE_SPINLOCK_MSM=y

CONFIG_IOMMU_IO_PGTABLE_FAST=y

CONFIG_IOMMU_IO_PGTABLE_FAST_SELFTEST=y

drivers/clk/qcom/clk-smd-rpm.c

+51 −4
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/mfd/qcom-rpm.h>



#include "clk-voter.h"



#define QCOM_RPM_KEY_SOFTWARE_ENABLE			0x6e657773

#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY	0x62636370

#define QCOM_RPM_SMD_KEY_RATE				0x007a484b
@@ -603,7 +605,7 @@ DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); 
DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_periph_clk, cnoc_periph_a_clk,

						QCOM_SMD_RPM_BUS_CLK, 0);

DEFINE_CLK_SMD_RPM(msmfalcon, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);

DEFINE_CLK_SMD_RPM(msmfalcon, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,

DEFINE_CLK_SMD_RPM(msmfalcon, mmssnoc_axi_clk, mmssnoc_axi_a_clk,

						   QCOM_SMD_RPM_MMAXI_CLK, 0);

DEFINE_CLK_SMD_RPM(msmfalcon, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);

DEFINE_CLK_SMD_RPM(msmfalcon, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
@@ -624,6 +626,27 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin, 
							ln_bb_clk2_pin_ao, 0x2);

DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin,

							ln_bb_clk3_pin_ao, 0x3);

/* Voter clocks */

static DEFINE_CLK_VOTER(bimc_msmbus_clk, bimc_clk, LONG_MAX);

static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, bimc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(cnoc_msmbus_clk, cnoc_clk, LONG_MAX);

static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, cnoc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(snoc_msmbus_clk, snoc_clk, LONG_MAX);

static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, snoc_a_clk, LONG_MAX);

static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, cnoc_periph_a_clk,

						LONG_MAX);

static DEFINE_CLK_VOTER(mcd_ce1_clk, ce1_clk, 85710000);

static DEFINE_CLK_VOTER(qcedev_ce1_clk, ce1_clk, 85710000);

static DEFINE_CLK_VOTER(qcrypto_ce1_clk, ce1_clk, 85710000);

static DEFINE_CLK_VOTER(qseecom_ce1_clk, ce1_clk, 85710000);

static DEFINE_CLK_VOTER(scm_ce1_clk, ce1_clk, 85710000);



static DEFINE_CLK_BRANCH_VOTER(cxo_dwc3_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, cxo);

static DEFINE_CLK_BRANCH_VOTER(cxo_pil_cdsp_clk, cxo);



static struct clk_hw *msmfalcon_clks[] = {

	[RPM_XO_CLK_SRC]	= &msmfalcon_cxo.hw,

	[RPM_XO_A_CLK_SRC]	= &msmfalcon_cxo_a.hw,
@@ -639,8 +662,8 @@ static struct clk_hw *msmfalcon_clks[] = { 
	[RPM_AGGR2_NOC_A_CLK]	= &msmfalcon_aggre2_noc_a_clk.hw,

	[RPM_CNOC_CLK]		= &msmfalcon_cnoc_clk.hw,

	[RPM_CNOC_A_CLK]	= &msmfalcon_cnoc_a_clk.hw,

	[RPM_MMAXI_CLK]		= &msmfalcon_mmssnoc_axi_rpm_clk.hw,

	[RPM_MMAXI_A_CLK]	= &msmfalcon_mmssnoc_axi_rpm_a_clk.hw,

	[RPM_MMAXI_CLK]		= &msmfalcon_mmssnoc_axi_clk.hw,

	[RPM_MMAXI_A_CLK]	= &msmfalcon_mmssnoc_axi_a_clk.hw,

	[RPM_IPA_CLK]		= &msmfalcon_ipa_clk.hw,

	[RPM_IPA_A_CLK]		= &msmfalcon_ipa_a_clk.hw,

	[RPM_CE1_CLK]		= &msmfalcon_ce1_clk.hw,
@@ -661,6 +684,25 @@ static struct clk_hw *msmfalcon_clks[] = { 
	[RPM_LN_BB_CLK3_PIN_AO] = &msmfalcon_ln_bb_clk3_pin_ao.hw,

	[RPM_CNOC_PERIPH_CLK]	= &msmfalcon_cnoc_periph_clk.hw,

	[RPM_CNOC_PERIPH_A_CLK] = &msmfalcon_cnoc_periph_a_clk.hw,



	/* Voter Clocks */

	[BIMC_MSMBUS_CLK]	= &bimc_msmbus_clk.hw,

	[BIMC_MSMBUS_A_CLK]	= &bimc_msmbus_a_clk.hw,

	[CNOC_MSMBUS_CLK]	= &cnoc_msmbus_clk.hw,

	[CNOC_MSMBUS_A_CLK]	= &cnoc_msmbus_a_clk.hw,

	[MCD_CE1_CLK]		= &mcd_ce1_clk.hw,

	[QCEDEV_CE1_CLK]	= &qcedev_ce1_clk.hw,

	[QCRYPTO_CE1_CLK]	= &qcrypto_ce1_clk.hw,

	[QSEECOM_CE1_CLK]	= &qseecom_ce1_clk.hw,

	[SCM_CE1_CLK]		= &scm_ce1_clk.hw,

	[SNOC_MSMBUS_CLK]	= &snoc_msmbus_clk.hw,

	[SNOC_MSMBUS_A_CLK]	= &snoc_msmbus_a_clk.hw,

	[CXO_DWC3_CLK]		= &cxo_dwc3_clk.hw,

	[CXO_LPM_CLK]		= &cxo_lpm_clk.hw,

	[CXO_OTG_CLK]		= &cxo_otg_clk.hw,

	[CXO_PIL_LPASS_CLK]	= &cxo_pil_lpass_clk.hw,

	[CXO_PIL_CDSP_CLK]	= &cxo_pil_cdsp_clk.hw,

	[CNOC_PERIPH_KEEPALIVE_A_CLK] = &cnoc_periph_keepalive_a_clk.hw,

};



static const struct rpm_smd_clk_desc rpm_clk_msmfalcon = {
@@ -757,9 +799,14 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) 
	/* Keep an active vote on CXO in case no other driver votes for it */

	if (is_8996)

		clk_prepare_enable(msm8996_cxo_a.hw.clk);

	else if (is_falcon)

	else if (is_falcon) {

		clk_prepare_enable(msmfalcon_cxo_a.hw.clk);



		/* Hold an active set vote for the cnoc_periph resource */

		clk_set_rate(cnoc_periph_keepalive_a_clk.hw.clk, 19200000);

		clk_prepare_enable(cnoc_periph_keepalive_a_clk.hw.clk);

	}



	dev_info(&pdev->dev, "Registered RPM clocks\n");



	return 0;

drivers/clk/qcom/common.c

+24 −7
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2014, 2016, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -177,7 +177,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk); 
int qcom_cc_really_probe(struct platform_device *pdev,

			 const struct qcom_cc_desc *desc, struct regmap *regmap)

{

	int i, ret;

	int i = 0, ret, j = 0;

	struct device *dev = &pdev->dev;

	struct clk *clk;

	struct clk_onecell_data *data;
@@ -187,8 +187,10 @@ int qcom_cc_really_probe(struct platform_device *pdev, 
	struct gdsc_desc *scd;

	size_t num_clks = desc->num_clks;

	struct clk_regmap **rclks = desc->clks;

	struct clk_hw **hw_clks = desc->hwclks;



	cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,

	cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) *

			(num_clks + desc->num_hwclks),

			  GFP_KERNEL);

	if (!cc)

		return -ENOMEM;
@@ -196,17 +198,32 @@ int qcom_cc_really_probe(struct platform_device *pdev, 
	clks = cc->clks;

	data = &cc->data;

	data->clks = clks;

	data->clk_num = num_clks;

	data->clk_num = num_clks + desc->num_hwclks;



	for (i = 0; i < num_clks; i++) {

		if (!rclks[i]) {

	for (i = 0; i < desc->num_hwclks; i++) {

		if (!hw_clks[i]) {

			clks[i] = ERR_PTR(-ENOENT);

			continue;

		}

		clk = devm_clk_register_regmap(dev, rclks[i]);

		clk = devm_clk_register(dev, hw_clks[i]);

		if (IS_ERR(clk))

			return PTR_ERR(clk);

		clks[i] = clk;

		pr_debug("Index for hw_clocks %d added %s\n", i,

							__clk_get_name(clk));

	}



	for (j = i; j < num_clks; j++) {

		if (!rclks[j]) {

			clks[j] = ERR_PTR(-ENOENT);

			continue;

		}

		clk = devm_clk_register_regmap(dev, rclks[j]);

		if (IS_ERR(clk))

			return PTR_ERR(clk);

		clks[j] = clk;

		pr_debug("Index for Regmap clocks %d added %s\n", j,

							__clk_get_name(clk));

	}



	ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);