Loading drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_bridge.c +9 −3 Original line number Diff line number Diff line Loading @@ -578,6 +578,9 @@ static void _sde_hdmi_bridge_disable(struct drm_bridge *bridge) display->sink_hdcp_ver = SDE_HDMI_HDCP_NONE; display->sink_hdcp22_support = false; if (sde_hdmi_tx_is_hdcp_enabled(display)) sde_hdmi_hdcp_off(display); sde_hdmi_clear_hdr_info(bridge); mutex_unlock(&display->display_lock); } Loading @@ -592,9 +595,6 @@ static void _sde_hdmi_bridge_post_disable(struct drm_bridge *bridge) sde_hdmi_notify_clients(display, display->connected); if (sde_hdmi_tx_is_hdcp_enabled(display)) sde_hdmi_hdcp_off(display); sde_hdmi_audio_off(hdmi); DRM_DEBUG("power down"); Loading @@ -603,10 +603,16 @@ static void _sde_hdmi_bridge_post_disable(struct drm_bridge *bridge) if (phy) phy->funcs->powerdown(phy); /* HDMI teardown sequence */ sde_hdmi_ctrl_reset(hdmi); if (hdmi->power_on) { _sde_hdmi_bridge_power_off(bridge); hdmi->power_on = false; } /* Powering-on the controller for HPD */ sde_hdmi_ctrl_cfg(hdmi, 1); } static void _sde_hdmi_bridge_set_avi_infoframe(struct hdmi *hdmi, Loading drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_hdcp2p2.c +8 −2 Original line number Diff line number Diff line Loading @@ -234,10 +234,16 @@ static void sde_hdmi_hdcp2p2_off(void *input) flush_kthread_worker(&ctrl->worker); sde_hdmi_hdcp2p2_ddc_disable((void *)ctrl->init_data.cb_data); cdata.context = input; sde_hdmi_hdcp2p2_wakeup(&cdata); /* There could be upto one frame delay * between the time encryption disable is * requested till the time we get encryption * disabled interrupt */ msleep(20); sde_hdmi_hdcp2p2_ddc_disable((void *)ctrl->init_data.cb_data); } static int sde_hdmi_hdcp2p2_authenticate(void *input) Loading drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_util.c +72 −0 Original line number Diff line number Diff line Loading @@ -681,6 +681,78 @@ static void _sde_hdmi_scrambler_ddc_reset(struct hdmi *hdmi) hdmi_write(hdmi, REG_HDMI_SCRAMBLER_STATUS_DDC_CTRL, reg_val); } void sde_hdmi_ctrl_cfg(struct hdmi *hdmi, bool power_on) { uint32_t ctrl = 0; unsigned long flags; spin_lock_irqsave(&hdmi->reg_lock, flags); ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); if (power_on) ctrl |= HDMI_CTRL_ENABLE; else ctrl &= ~HDMI_CTRL_ENABLE; hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); spin_unlock_irqrestore(&hdmi->reg_lock, flags); HDMI_UTIL_DEBUG("HDMI Core: %s, HDMI_CTRL=0x%08x\n", power_on ? "Enable" : "Disable", ctrl); } static void sde_hdmi_clear_pkt_send(struct hdmi *hdmi) { uint32_t reg_val; /* Clear audio sample send */ reg_val = hdmi_read(hdmi, HDMI_AUDIO_PKT_CTRL); reg_val &= ~BIT(0); hdmi_write(hdmi, HDMI_AUDIO_PKT_CTRL, reg_val); /* Clear sending VBI ctrl packets */ reg_val = hdmi_read(hdmi, HDMI_VBI_PKT_CTRL); reg_val &= ~(BIT(4) | BIT(8) | BIT(12)); hdmi_write(hdmi, HDMI_VBI_PKT_CTRL, reg_val); /* Clear sending infoframe packets */ reg_val = hdmi_read(hdmi, HDMI_INFOFRAME_CTRL0); reg_val &= ~(BIT(0) | BIT(4) | BIT(8) | BIT(12) | BIT(15) | BIT(19)); hdmi_write(hdmi, HDMI_INFOFRAME_CTRL0, reg_val); /* Clear sending general ctrl packets */ reg_val = hdmi_read(hdmi, HDMI_GEN_PKT_CTRL); reg_val &= ~(BIT(0) | BIT(4)); hdmi_write(hdmi, HDMI_GEN_PKT_CTRL, reg_val); } void sde_hdmi_ctrl_reset(struct hdmi *hdmi) { uint32_t reg_val; /* Assert HDMI CTRL SW reset */ reg_val = hdmi_read(hdmi, HDMI_CTRL_SW_RESET); reg_val |= BIT(0); hdmi_write(hdmi, HDMI_CTRL_SW_RESET, reg_val); /* disable the controller and put to known state */ sde_hdmi_ctrl_cfg(hdmi, 0); /* disable the audio engine */ reg_val = hdmi_read(hdmi, HDMI_AUDIO_CFG); reg_val &= ~BIT(0); hdmi_write(hdmi, HDMI_AUDIO_CFG, reg_val); /* clear sending packets to sink */ sde_hdmi_clear_pkt_send(hdmi); /* De-assert HDMI CTRL SW reset */ reg_val = hdmi_read(hdmi, HDMI_CTRL_SW_RESET); reg_val &= ~BIT(0); hdmi_write(hdmi, HDMI_CTRL_SW_RESET, reg_val); } void _sde_hdmi_scrambler_ddc_disable(void *hdmi_display) { struct sde_hdmi *display = (struct sde_hdmi *)hdmi_display; Loading drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_util.h +3 −0 Original line number Diff line number Diff line Loading @@ -198,4 +198,7 @@ int sde_hdmi_sink_dc_support(struct drm_connector *connector, struct drm_display_mode *mode); u8 sde_hdmi_hdr_get_ops(u8 curr_state, u8 new_state); void sde_hdmi_ctrl_reset(struct hdmi *hdmi); void sde_hdmi_ctrl_cfg(struct hdmi *hdmi, bool power_on); #endif /* _SDE_HDMI_UTIL_H_ */ Loading
drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_bridge.c +9 −3 Original line number Diff line number Diff line Loading @@ -578,6 +578,9 @@ static void _sde_hdmi_bridge_disable(struct drm_bridge *bridge) display->sink_hdcp_ver = SDE_HDMI_HDCP_NONE; display->sink_hdcp22_support = false; if (sde_hdmi_tx_is_hdcp_enabled(display)) sde_hdmi_hdcp_off(display); sde_hdmi_clear_hdr_info(bridge); mutex_unlock(&display->display_lock); } Loading @@ -592,9 +595,6 @@ static void _sde_hdmi_bridge_post_disable(struct drm_bridge *bridge) sde_hdmi_notify_clients(display, display->connected); if (sde_hdmi_tx_is_hdcp_enabled(display)) sde_hdmi_hdcp_off(display); sde_hdmi_audio_off(hdmi); DRM_DEBUG("power down"); Loading @@ -603,10 +603,16 @@ static void _sde_hdmi_bridge_post_disable(struct drm_bridge *bridge) if (phy) phy->funcs->powerdown(phy); /* HDMI teardown sequence */ sde_hdmi_ctrl_reset(hdmi); if (hdmi->power_on) { _sde_hdmi_bridge_power_off(bridge); hdmi->power_on = false; } /* Powering-on the controller for HPD */ sde_hdmi_ctrl_cfg(hdmi, 1); } static void _sde_hdmi_bridge_set_avi_infoframe(struct hdmi *hdmi, Loading
drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_hdcp2p2.c +8 −2 Original line number Diff line number Diff line Loading @@ -234,10 +234,16 @@ static void sde_hdmi_hdcp2p2_off(void *input) flush_kthread_worker(&ctrl->worker); sde_hdmi_hdcp2p2_ddc_disable((void *)ctrl->init_data.cb_data); cdata.context = input; sde_hdmi_hdcp2p2_wakeup(&cdata); /* There could be upto one frame delay * between the time encryption disable is * requested till the time we get encryption * disabled interrupt */ msleep(20); sde_hdmi_hdcp2p2_ddc_disable((void *)ctrl->init_data.cb_data); } static int sde_hdmi_hdcp2p2_authenticate(void *input) Loading
drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_util.c +72 −0 Original line number Diff line number Diff line Loading @@ -681,6 +681,78 @@ static void _sde_hdmi_scrambler_ddc_reset(struct hdmi *hdmi) hdmi_write(hdmi, REG_HDMI_SCRAMBLER_STATUS_DDC_CTRL, reg_val); } void sde_hdmi_ctrl_cfg(struct hdmi *hdmi, bool power_on) { uint32_t ctrl = 0; unsigned long flags; spin_lock_irqsave(&hdmi->reg_lock, flags); ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); if (power_on) ctrl |= HDMI_CTRL_ENABLE; else ctrl &= ~HDMI_CTRL_ENABLE; hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); spin_unlock_irqrestore(&hdmi->reg_lock, flags); HDMI_UTIL_DEBUG("HDMI Core: %s, HDMI_CTRL=0x%08x\n", power_on ? "Enable" : "Disable", ctrl); } static void sde_hdmi_clear_pkt_send(struct hdmi *hdmi) { uint32_t reg_val; /* Clear audio sample send */ reg_val = hdmi_read(hdmi, HDMI_AUDIO_PKT_CTRL); reg_val &= ~BIT(0); hdmi_write(hdmi, HDMI_AUDIO_PKT_CTRL, reg_val); /* Clear sending VBI ctrl packets */ reg_val = hdmi_read(hdmi, HDMI_VBI_PKT_CTRL); reg_val &= ~(BIT(4) | BIT(8) | BIT(12)); hdmi_write(hdmi, HDMI_VBI_PKT_CTRL, reg_val); /* Clear sending infoframe packets */ reg_val = hdmi_read(hdmi, HDMI_INFOFRAME_CTRL0); reg_val &= ~(BIT(0) | BIT(4) | BIT(8) | BIT(12) | BIT(15) | BIT(19)); hdmi_write(hdmi, HDMI_INFOFRAME_CTRL0, reg_val); /* Clear sending general ctrl packets */ reg_val = hdmi_read(hdmi, HDMI_GEN_PKT_CTRL); reg_val &= ~(BIT(0) | BIT(4)); hdmi_write(hdmi, HDMI_GEN_PKT_CTRL, reg_val); } void sde_hdmi_ctrl_reset(struct hdmi *hdmi) { uint32_t reg_val; /* Assert HDMI CTRL SW reset */ reg_val = hdmi_read(hdmi, HDMI_CTRL_SW_RESET); reg_val |= BIT(0); hdmi_write(hdmi, HDMI_CTRL_SW_RESET, reg_val); /* disable the controller and put to known state */ sde_hdmi_ctrl_cfg(hdmi, 0); /* disable the audio engine */ reg_val = hdmi_read(hdmi, HDMI_AUDIO_CFG); reg_val &= ~BIT(0); hdmi_write(hdmi, HDMI_AUDIO_CFG, reg_val); /* clear sending packets to sink */ sde_hdmi_clear_pkt_send(hdmi); /* De-assert HDMI CTRL SW reset */ reg_val = hdmi_read(hdmi, HDMI_CTRL_SW_RESET); reg_val &= ~BIT(0); hdmi_write(hdmi, HDMI_CTRL_SW_RESET, reg_val); } void _sde_hdmi_scrambler_ddc_disable(void *hdmi_display) { struct sde_hdmi *display = (struct sde_hdmi *)hdmi_display; Loading
drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_util.h +3 −0 Original line number Diff line number Diff line Loading @@ -198,4 +198,7 @@ int sde_hdmi_sink_dc_support(struct drm_connector *connector, struct drm_display_mode *mode); u8 sde_hdmi_hdr_get_ops(u8 curr_state, u8 new_state); void sde_hdmi_ctrl_reset(struct hdmi *hdmi); void sde_hdmi_ctrl_cfg(struct hdmi *hdmi, bool power_on); #endif /* _SDE_HDMI_UTIL_H_ */