Loading drivers/gpu/drm/msm/dba_bridge.c +3 −0 Original line number Diff line number Diff line Loading @@ -232,6 +232,9 @@ static void _dba_bridge_post_disable(struct drm_bridge *bridge) return; } if (d_bridge->cont_splash_enabled) d_bridge->cont_splash_enabled = false; if (d_bridge->ops.power_on) { rc = d_bridge->ops.power_on(d_bridge->dba_ctx, false, 0); if (rc) Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.c +55 −5 Original line number Diff line number Diff line Loading @@ -176,6 +176,18 @@ static int dsi_display_ctrl_power_on(struct dsi_display *display) if (display->cont_splash_enabled) { pr_debug("skip ctrl power on\n"); for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl) continue; if (!ctrl->ctrl->current_state.pwr_enabled) { ctrl->ctrl->pwr_info.host_pwr.refcount++; ctrl->ctrl->pwr_info.digital.refcount++; ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_VREG_ON; ctrl->ctrl->current_state.pwr_enabled = true; } } return rc; } Loading Loading @@ -239,6 +251,16 @@ static int dsi_display_phy_power_on(struct dsi_display *display) /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip phy power on\n"); for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl) continue; if (!ctrl->phy->power_state) { ctrl->phy->pwr_info.digital.refcount++; ctrl->phy->pwr_info.phy_pwr.refcount++; ctrl->phy->power_state = true; } } return rc; } Loading Loading @@ -298,9 +320,25 @@ static int dsi_display_ctrl_core_clk_on(struct dsi_display *display) int i; struct dsi_display_ctrl *m_ctrl, *ctrl; m_ctrl = &display->ctrl[display->clk_master_idx]; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip core clk on calling\n"); m_ctrl->ctrl->current_state.pwr_enabled = true; m_ctrl->ctrl->current_state.core_clk_enabled = true; m_ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_CORE_CLK_ON; for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl || (ctrl == m_ctrl)) continue; ctrl->ctrl->current_state.pwr_enabled = true; ctrl->ctrl->current_state.core_clk_enabled = true; ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_CORE_CLK_ON; } return rc; } Loading @@ -309,9 +347,6 @@ static int dsi_display_ctrl_core_clk_on(struct dsi_display *display) * be enabled before the other controller. Master controller in the * clock context refers to the controller that sources the clock. */ m_ctrl = &display->ctrl[display->clk_master_idx]; rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_CORE_CLK_ON); if (rc) { pr_err("[%s] failed to turn on clocks, rc=%d\n", Loading Loading @@ -346,9 +381,26 @@ static int dsi_display_ctrl_link_clk_on(struct dsi_display *display) int i; struct dsi_display_ctrl *m_ctrl, *ctrl; m_ctrl = &display->ctrl[display->clk_master_idx]; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip ctrl link clk on calling\n"); m_ctrl->ctrl->current_state.pwr_enabled = true; m_ctrl->ctrl->current_state.core_clk_enabled = true; m_ctrl->ctrl->current_state.link_clk_enabled = true; m_ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_LINK_CLK_ON; for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl || (ctrl == m_ctrl)) continue; ctrl->ctrl->current_state.pwr_enabled = true; ctrl->ctrl->current_state.core_clk_enabled = true; ctrl->ctrl->current_state.link_clk_enabled = true; ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_LINK_CLK_ON; } return rc; } Loading @@ -358,8 +410,6 @@ static int dsi_display_ctrl_link_clk_on(struct dsi_display *display) * clock context refers to the controller that sources the clock. */ m_ctrl = &display->ctrl[display->clk_master_idx]; rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &display->clock_info.src_clks); if (rc) { Loading Loading
drivers/gpu/drm/msm/dba_bridge.c +3 −0 Original line number Diff line number Diff line Loading @@ -232,6 +232,9 @@ static void _dba_bridge_post_disable(struct drm_bridge *bridge) return; } if (d_bridge->cont_splash_enabled) d_bridge->cont_splash_enabled = false; if (d_bridge->ops.power_on) { rc = d_bridge->ops.power_on(d_bridge->dba_ctx, false, 0); if (rc) Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.c +55 −5 Original line number Diff line number Diff line Loading @@ -176,6 +176,18 @@ static int dsi_display_ctrl_power_on(struct dsi_display *display) if (display->cont_splash_enabled) { pr_debug("skip ctrl power on\n"); for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl) continue; if (!ctrl->ctrl->current_state.pwr_enabled) { ctrl->ctrl->pwr_info.host_pwr.refcount++; ctrl->ctrl->pwr_info.digital.refcount++; ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_VREG_ON; ctrl->ctrl->current_state.pwr_enabled = true; } } return rc; } Loading Loading @@ -239,6 +251,16 @@ static int dsi_display_phy_power_on(struct dsi_display *display) /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip phy power on\n"); for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl) continue; if (!ctrl->phy->power_state) { ctrl->phy->pwr_info.digital.refcount++; ctrl->phy->pwr_info.phy_pwr.refcount++; ctrl->phy->power_state = true; } } return rc; } Loading Loading @@ -298,9 +320,25 @@ static int dsi_display_ctrl_core_clk_on(struct dsi_display *display) int i; struct dsi_display_ctrl *m_ctrl, *ctrl; m_ctrl = &display->ctrl[display->clk_master_idx]; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip core clk on calling\n"); m_ctrl->ctrl->current_state.pwr_enabled = true; m_ctrl->ctrl->current_state.core_clk_enabled = true; m_ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_CORE_CLK_ON; for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl || (ctrl == m_ctrl)) continue; ctrl->ctrl->current_state.pwr_enabled = true; ctrl->ctrl->current_state.core_clk_enabled = true; ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_CORE_CLK_ON; } return rc; } Loading @@ -309,9 +347,6 @@ static int dsi_display_ctrl_core_clk_on(struct dsi_display *display) * be enabled before the other controller. Master controller in the * clock context refers to the controller that sources the clock. */ m_ctrl = &display->ctrl[display->clk_master_idx]; rc = dsi_ctrl_set_power_state(m_ctrl->ctrl, DSI_CTRL_POWER_CORE_CLK_ON); if (rc) { pr_err("[%s] failed to turn on clocks, rc=%d\n", Loading Loading @@ -346,9 +381,26 @@ static int dsi_display_ctrl_link_clk_on(struct dsi_display *display) int i; struct dsi_display_ctrl *m_ctrl, *ctrl; m_ctrl = &display->ctrl[display->clk_master_idx]; /* early return for splash enabled case */ if (display->cont_splash_enabled) { pr_debug("skip ctrl link clk on calling\n"); m_ctrl->ctrl->current_state.pwr_enabled = true; m_ctrl->ctrl->current_state.core_clk_enabled = true; m_ctrl->ctrl->current_state.link_clk_enabled = true; m_ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_LINK_CLK_ON; for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->ctrl || (ctrl == m_ctrl)) continue; ctrl->ctrl->current_state.pwr_enabled = true; ctrl->ctrl->current_state.core_clk_enabled = true; ctrl->ctrl->current_state.link_clk_enabled = true; ctrl->ctrl->current_state.power_state = DSI_CTRL_POWER_LINK_CLK_ON; } return rc; } Loading @@ -358,8 +410,6 @@ static int dsi_display_ctrl_link_clk_on(struct dsi_display *display) * clock context refers to the controller that sources the clock. */ m_ctrl = &display->ctrl[display->clk_master_idx]; rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &display->clock_info.src_clks); if (rc) { Loading