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Commit 6e4ffe07 authored by Oleg Perelet's avatar Oleg Perelet Committed by Kyle Yan
Browse files

msm: kgsl: Add gcc_gpu_iref_clk to list of GPU clocks 



GPU will vote off gcc_gpu_iref_clk when going to low power modes.

CRs-Fixed: 1024948
Change-Id: I13b7a70f1fa748f2f4cdfb485dda2f7857e0b3d2
Signed-off-by: default avatarOleg Perelet <operelet@codeaurora.org>
parent a0605c53

Documentation/devicetree/bindings/gpu/adreno.txt

+2 −1
Original line number Diff line number Diff line
@@ -25,7 +25,8 @@ Required properties: 
			order as the clocks property.

				Current values of clock-names are:

				"src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",

				"alt_mem_iface_clk", "rbbmtimer_clk",  "alwayson_clk"

				"alt_mem_iface_clk", "rbbmtimer_clk",  "alwayson_clk",

				"iref_clk"

				"core_clk" and "iface_clk" are required and others are optional



- qcom,base-leakage-coefficient: Dynamic leakage coefficient.

arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi

+4 −2
Original line number Diff line number Diff line
@@ -84,10 +84,12 @@ 
			<&clock_gcc clk_gcc_bimc_gfx_clk>,

			<&clock_gcc clk_gcc_gpu_bimc_gfx_clk>,

			<&clock_gpu clk_gpucc_gfx3d_isense_clk>,

			<&clock_gpu clk_gpucc_rbcpr_clk>;

			<&clock_gpu clk_gpucc_rbcpr_clk>,

			<&clock_gcc clk_gcc_gpu_iref_clk>;



		clock-names = "core_clk", "iface_clk", "rbbmtimer_clk",

			"mem_clk", "mem_iface_clk", "isense_clk", "rbcpr_clk";

			"mem_clk", "mem_iface_clk", "isense_clk", "rbcpr_clk",

			"iref_clk";



		/* Bus Scale Settings */

		qcom,gpubw-dev = <&gpubw>;

drivers/gpu/msm/kgsl_pwrctrl.c

+2 −1
Original line number Diff line number Diff line
@@ -64,7 +64,8 @@ static const char * const clocks[] = { 
	"gtcu_iface_clk",

	"alwayson_clk",

	"isense_clk",

	"rbcpr_clk"

	"rbcpr_clk",

	"iref_clk"

};



static unsigned int ib_votes[KGSL_MAX_BUSLEVELS];

drivers/gpu/msm/kgsl_pwrctrl.h

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ 


#define KGSL_PWR_ON	0xFFFF



#define KGSL_MAX_CLKS 13

#define KGSL_MAX_CLKS 14

#define KGSL_MAX_REGULATORS 2



#define KGSL_MAX_PWRLEVELS 10