ath10k: Enable SRRI/DRRI support on ddr

The SRRI/DRRI can be read from DDR instead of doing an
actual hardware read. Host allocates non cached memory
on ddr and sends the physical address of this memory to
the CE hardware. The hardware updates the RRI on this
particular location. Target registers are not accessible
during CSS shutdown while target is in idle mode. Direct
access to SRRI/DRRI can lead to NOC error in target idle
state. Read SRRI/DRRI from DDR location instead of
direct target read.

Change-Id: Iae3772fb6408469c5f9db8a9210d3ab6ea35eccf
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>