Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5c575fbb authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Gerrit - the friendly Code Review server
Browse files

msm: mdss: add support to set the parent of DP pixel clock RCG 



DP pixel RCG clock has multiple parents as per the clock plan
and doesn't have a fixed frequency table defined in the common
clock driver. For targets which use common clock framework like
SDM660, the parent of such RCGs need to be set by the client
itself. Add support to set the parent of DP pixel RCG clock.

Change-Id: I00ec66725ab40de28db84593c111d402a7bd7ac8
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent c9deb68c

drivers/video/fbdev/msm/mdss_dp.c

+21 −0
Original line number Diff line number Diff line
@@ -338,7 +338,25 @@ static int mdss_dp_clk_init(struct mdss_dp_drv_pdata *dp_drv, 
			goto ctrl_get_error;

		}



		dp_drv->pixel_clk_rcg = devm_clk_get(dev, "pixel_clk_rcg");

		if (IS_ERR(dp_drv->pixel_clk_rcg)) {

			pr_debug("%s: Unable to get DP pixel clk RCG\n",

				__func__);

			dp_drv->pixel_clk_rcg = NULL;

		}



		dp_drv->pixel_parent = devm_clk_get(dev,

			"pixel_parent");

		if (IS_ERR(dp_drv->pixel_parent)) {

			pr_debug("%s: Unable to get DP pixel RCG parent\n",

				__func__);

			dp_drv->pixel_parent = NULL;

		}

	} else {

		if (dp_drv->pixel_parent)

			devm_clk_put(dev, dp_drv->pixel_parent);

		if (dp_drv->pixel_clk_rcg)

			devm_clk_put(dev, dp_drv->pixel_clk_rcg);

		msm_dss_put_clk(ctrl_power_data->clk_config,

					ctrl_power_data->num_clk);

		msm_dss_put_clk(core_power_data->clk_config,
@@ -1258,6 +1276,9 @@ static int mdss_dp_enable_mainlink_clocks(struct mdss_dp_drv_pdata *dp) 
{

	int ret = 0;



	if (dp->pixel_clk_rcg && dp->pixel_parent)

		clk_set_parent(dp->pixel_clk_rcg, dp->pixel_parent);



	mdss_dp_set_clock_rate(dp, "ctrl_link_clk",

		(dp->link_rate * DP_LINK_RATE_MULTIPLIER) / DP_KHZ_TO_HZ);

drivers/video/fbdev/msm/mdss_dp.h

+4 −0
Original line number Diff line number Diff line
@@ -489,6 +489,10 @@ struct mdss_dp_drv_pdata { 
	struct edp_edid edid;

	struct dpcd_cap dpcd;



	/* DP Pixel clock RCG and PLL parent */

	struct clk *pixel_clk_rcg;

	struct clk *pixel_parent;



	/* regulators */

	struct dss_module_power power_data[DP_MAX_PM];

	struct dp_pinctrl_res pin_res;