drm/msm/sde: add driver for sde support

Qualcomm Technologies, Inc. SDE KMS

Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user

interface to different panel interfaces. SDE driver is the core of

display subsystem which manage all data paths to different panel interfaces.

Required properties

- compatible: Must be "qcom,sde-kms"

- reg: Offset and length of the register set for the device.

- reg-names : Names to refer to register sets related to this device

- clocks: List of Phandles for clock device nodes

    needed by the device.

- clock-names: List of clock names needed by the device.

- mmagic-supply: Phandle for mmagic mdss supply regulator device node.

- vdd-supply: Phandle for vdd regulator device node.

- interrupt-parent: Must be core interrupt controller.

- interrupts: Interrupt associated with MDSS.

- interrupt-controller: Mark the device node as an interrupt controller.

- #interrupt-cells: Should be one. The first cell is interrupt number.

- iommus: Specifies the SID's used by this context bank.

Please refer to ../../interrupt-controller/interrupts.txt for a general

description of interrupt bindings.

Example:

  mdss_mdp: qcom,mdss_mdp@900000 {

    compatible = "qcom,sde-kms";

    reg = <0x00900000 0x90000>,

          <0x009b0000 0x1040>,

          <0x009b8000 0x1040>;

    reg-names = "mdp_phys",

      "vbif_phys",

      "vbif_nrt_phys";

    clocks = <&clock_mmss clk_mdss_ahb_clk>,

      <&clock_mmss clk_mdss_axi_clk>,

      <&clock_mmss clk_mdp_clk_src>,

      <&clock_mmss clk_mdss_mdp_vote_clk>,

      <&clock_mmss clk_smmu_mdp_axi_clk>,

      <&clock_mmss clk_mmagic_mdss_axi_clk>,

      <&clock_mmss clk_mdss_vsync_clk>;

    clock-names = "iface_clk",

      "bus_clk",

      "core_clk_src",

      "core_clk",

      "iommu_clk",

      "mmagic_clk",

      "vsync_clk";

    mmagic-supply = <&gdsc_mmagic_mdss>;

    vdd-supply = <&gdsc_mdss>;

    interrupt-parent = <&intc>;

    interrupts = <0 83 0>;

    interrupt-controller;

    #interrupt-cells = <1>;

    iommus = <&mdp_smmu 0>;

  };

	mdp/mdp5/mdp5_kms.o \

	mdp/mdp5/mdp5_plane.o \

	mdp/mdp5/mdp5_smp.o \

	sde/sde_crtc.o \

	sde/sde_encoder.o \

	sde/sde_irq.o \

	sde/sde_kms.o \

	sde/sde_plane.o \

	msm_atomic.o \

	msm_drv.o \

	msm_fb.o \

endif

obj-$(CONFIG_DRM_MSM)	+= msm.o

obj-$(CONFIG_DRM_MSM) += sde/sde_hw_catalog.o \

	sde/sde_hw_catalog_8996.o \

	sde/sde_hw_cdm.o \

	sde/sde_hw_dspp.o \

	sde/sde_hw_intf.o \

	sde/sde_hw_lm.o \

	sde/sde_hw_mdp_ctl.o \

	sde/sde_hw_mdp_util.o \

	sde/sde_hw_sspp.o \

	sde/sde_hw_wb.o \

	sde/sde_hw_pingpong.o

	return 0;

}

#define KMS_MDP4 0

#define KMS_MDP5 1

#define KMS_SDE  2

static int get_mdp_ver(struct platform_device *pdev)

{

#ifdef CONFIG_OF

	static const struct of_device_id match_types[] = { {

		.compatible = "qcom,mdss_mdp",

		.data	= (void	*)5,

	}, {

		.data	= (void	*)KMS_MDP5,

	},

	{

		.compatible = "qcom,sde-kms",

		.data	= (void	*)KMS_SDE,

		/* end node */

	} };

	struct device *dev = &pdev->dev;

	if (match)

		return (int)(unsigned long)match->data;

#endif

	return 4;

	return KMS_MDP4;

}

#include <linux/of_address.h>

		goto fail;

	switch (get_mdp_ver(pdev)) {

	case 4:

	case KMS_MDP4:

		kms = mdp4_kms_init(dev);

		break;

	case 5:

	case KMS_MDP5:

		kms = mdp5_kms_init(dev);

		break;

	case KMS_SDE:

		kms = sde_kms_init(dev);

		break;

	default:

		kms = ERR_PTR(-ENODEV);

		break;

static const struct of_device_id dt_match[] = {

	{ .compatible = "qcom,mdp" },      /* mdp4 */

	{ .compatible = "qcom,mdss_mdp" }, /* mdp5 */

	{ .compatible = "qcom,sde-kms" },  /* sde  */

	{}

};

MODULE_DEVICE_TABLE(of, dt_match);

struct msm_gem_submit;

#define NUM_DOMAINS    2    /* one for KMS, then one per gpu core (?) */

#define MAX_CRTCS      8

#define MAX_PLANES     12

#define MAX_ENCODERS   8

#define MAX_BRIDGES    8

#define MAX_CONNECTORS 8

struct msm_file_private {

	/* currently we don't do anything useful with this.. but when

	struct msm_mmu *mmus[NUM_DOMAINS];

	unsigned int num_planes;

	struct drm_plane *planes[8];

	struct drm_plane *planes[MAX_PLANES];

	unsigned int num_crtcs;

	struct drm_crtc *crtcs[8];

	struct drm_crtc *crtcs[MAX_CRTCS];

	unsigned int num_encoders;

	struct drm_encoder *encoders[8];

	struct drm_encoder *encoders[MAX_ENCODERS];

	unsigned int num_bridges;

	struct drm_bridge *bridges[8];

	struct drm_bridge *bridges[MAX_BRIDGES];

	unsigned int num_connectors;

	struct drm_connector *connectors[8];

	struct drm_connector *connectors[MAX_CONNECTORS];

	/* Properties */

	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];

struct msm_kms *mdp4_kms_init(struct drm_device *dev);

struct msm_kms *mdp5_kms_init(struct drm_device *dev);

struct msm_kms *sde_kms_init(struct drm_device *dev);

#endif /* __MSM_KMS_H__ */