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Commit 28f64cb2 authored by Linux Build Service Account's avatar Linux Build Service Account
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Promotion of kernel.lnx.4.4-161103. 

CRs      Change ID                                   Subject
--------------------------------------------------------------------------------------------------------------
1084491   Ia9350b9c7810db7eb900957b4ce5dac046ab5e0d   ARM: dts: msm: Add qcom,dump-size entry for dumping CPU
1084491   I37ca3aae0471fcd60499615df77093d5b5451bf8   Documentation: arm: add cache DT bindings
1078910   I9cb454cebb74df291479cecc3533d2c684363f77   ion: disable system contig heap
1077179   I5bc6a5a46311206818d70567e31fd84adc0128be   leds: qpnp-flash-v2: Fix strobe control settings
1077868   Id568f76e03b93cf411366abf01ea857fb80ff1bf   ARM: dts: msm: correct cpu nodes information for msmtrit
1083761   Ib38ecabb3c4bf40fcf5ad368fbbdbe4c44edbf3b   msm: vidc: Scale bus bw along with venus clocks
1084236   I4c13601b0fded6de9d8f897c6d471c6a40c90e4d   sched/hmp: Automatically add children threads to colocat
1070067   I0d4b9f72a12e91b16f3844ac70db33b7de5e5263   usb_bam: Avoid uninitialized variable errors
1080024   I92bd53432a11241228d2e5ac89a3b20d19b05a31   CHROMIUM: dm: boot time specification of dm=
1049826   I3e11ca7f6df4bb0d928512f81f3e3dc40fed791a   msm: camera: cpp: Validate frame message before manipula
1080024   I952d86fd1475f0825f9be1386e3497b36127abd0   ANDROID: dm: Rebase on top of 4.1
1082476 1750919   I3a79950b76c1c38e487471f21dc60590b032dd3f   msm: vidc: Correct debugfs directory name
1080024   I4ba1043965d25ec444a833283392ac2394c845f3   Revert "init: do_mounts: Add a dummy definition for dm_t
1084009   Ie1a5038458b0b93dfec3e5bfc350686eb1f8eb1b   ASoC: wcd934x: Initialize mbhc pointer before access
1080688   Ia60fc3ecb5c2aba19effe1c8242f2d89fdef3ebd   ARM: dts: msm: specify SPI configuration for msmfalcon.
1083524   Ic26fa36bf84bce020ad07ad87de50e684dd7fa5a   ARM: dts: msm: Add initial support for msmcobalt V2 QRD
1075835 1075868   I06426109ab39d33e2b11514082c0bc989c4c8167   coresight: tmc: avoid null pointer dereference
1072541   If2b3e241076a4e0eeb87eeb4361398313fca6962   dwc3: gadget: Remove disabling events and ep0 from gadge
1081711   Iee908c56ec530569b35dafa060139e0428efc781   soc: qcom: scm: add check to avoid buffer overflow
1025311   Ie432af1fefc79f88ec67d212f8b9880355c4266d   cfg80211: support virtual interfaces with different beac
1043802   I3eb92f83b42b0fa28dc73f6e0d4f74ef50375855   ARM: dts: msm: add support for QBT1000 on msmcobalt
1082843   I6ab3992958a659995b7d5020287fd6e47e28f2a4   clk: msm: clock-debug: Print VDD level in clock_state tr
1082816   I475d1219ae62378a90c69642f2320149d0f13885   ASoc: wcd934x: correct MAD micbias setting
967547   I92b10e62be8129ead5859a285bf964ab0a3ae2fd   driver core: fix race between creating/querying glue dir
1084935   I31e8e0b5e9ae240ca031f625cf7c49f1bfe165d4   msm: secure_buffer: fix scm call argument layout
1074738   Ie7f8cee59b90f16f8a844d618a6f903b3e3c2f27   msm: mdss: lock mutex before setting backlight

Change-Id: Id13d60a1768a89563fa5209fc5fe3abfc2ea7bb0
CRs-Fixed: 1077179, 1075868, 1082476, 1083761, 1081711, 1043802, 1084935, 1049826, 1070067, 1082816, 1025311, 1074738, 1083524, 1075835, 1080024, 1750919, 1072541, 1084491, 1084009, 1077868, 967547, 1084236, 1080688, 1078910, 1082843
parents 65485bf0 8a4f90bd

Documentation/device-mapper/boot.txt

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+42 −0
Original line number Diff line number Diff line 
Boot time creation of mapped devices

===================================



It is possible to configure a device mapper device to act as the root

device for your system in two ways.



The first is to build an initial ramdisk which boots to a minimal

userspace which configures the device, then pivot_root(8) in to it.



For simple device mapper configurations, it is possible to boot directly

using the following kernel command line:



dm="<name> <uuid> <ro>,table line 1,...,table line n"



name = the name to associate with the device

	after boot, udev, if used, will use that name to label

	the device node.

uuid = may be 'none' or the UUID desired for the device.

ro = may be "ro" or "rw".  If "ro", the device and device table will be

	marked read-only.



Each table line may be as normal when using the dmsetup tool except for

two variations:

1. Any use of commas will be interpreted as a newline

2. Quotation marks cannot be escaped and cannot be used without

   terminating the dm= argument.



Unless renamed by udev, the device node created will be dm-0 as the

first minor number for the device-mapper is used during early creation.



Example

=======



- Booting to a linear array made up of user-mode linux block devices:



  dm="lroot none 0, 0 4096 linear 98:16 0, 4096 4096 linear 98:32 0" \

  root=/dev/dm-0



Will boot to a rw dm-linear target of 8192 sectors split across two

block devices identified by their major:minor numbers.  After boot, udev

will rename this target to /dev/mapper/lroot (depending on the rules).

No uuid was assigned.

Documentation/devicetree/bindings/arm/cache.txt

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+195 −0
Original line number Diff line number Diff line 
==========================================

ARM processors cache binding description

==========================================



Device tree bindings for ARM processor caches adhere to the cache bindings

described in [3], in section 3.8 for multi-level and shared caches.

On ARM based systems most of the cache properties related to cache

geometry are probeable in HW, hence, unless otherwise stated, the properties

defined in ePAPR for multi-level and shared caches are to be considered

optional by default.



On ARM, caches are either architected (directly controlled by the processor

through coprocessor instructions and tightly coupled with the processor

implementation) or unarchitected (controlled through a memory mapped

interface, implemented as a stand-alone IP external to the processor

implementation).



This document provides the device tree bindings for ARM architected caches.



- ARM architected cache node



	Description: must be a direct child of the cpu node. A system

		     can contain multiple architected cache nodes per cpu node,

		     linked through the next-level-cache phandle. The

		     next-level-cache property in the cpu node points to

		     the first level of architected cache for the CPU.

		     The next-level-cache property in architected cache nodes

		     points to the respective next level of caching in the

		     hierarchy. An architected cache node with an empty or

		     missing next-level-cache property represents the last

		     architected cache level for the CPU.

		     On ARM v7 and v8 architectures, the order in which cache

		     nodes are linked through the next-level-cache phandle must

		     follow the ordering specified in the processors CLIDR (v7)

		     and CLIDR_EL1 (v8) registers, as described in [1][2],

		     implying that a cache node pointed at by a

		     next-level-cache phandle must correspond to a level

		     defined in CLIDR (v7) and CLIDR_EL1 (v8) greater than the

		     one the cache node containing the next-level-cache

		     phandle corresponds to.



	Since on ARM most of the cache properties are probeable in HW the

	properties described in [3] - section 3.8 multi-level and shared

	caches - shall be considered optional, with the following properties

	updates, specific for the ARM architected cache node.



	- compatible

		Usage: Required

		Value type: <string>

		Definition: value shall be "arm,arch-cache".



	- interrupts

		Usage: Optional

		Value type: See definition

		Definition: standard device tree property [3] that defines

			    the interrupt line associated with the cache.

			    The property can be accompanied by an

			    interrupt-names property, as described in [4].



	- power-domain

		Usage: Optional

		Value type: phandle

		Definition: A phandle and power domain specifier as defined by

			    bindings of power controller specified by the

			    phandle [5].



	- qcom,dump-size

		Usage: Optional

		Value type: <integer>

		Definition: The memory size needed to contain a copy of the

			    cache data and associated tag ram.

			    size = nways * nsets * (bytes per cache line +

			                            bytes tag ram per line)



Example(dual-cluster big.LITTLE system 32-bit)



	cpus {

		#size-cells = <0>;

		#address-cells = <1>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0x0>;

			next-level-cache = <&L1_0>;



			L1_0: l1-cache {

				compatible = "arm,arch-cache";

				next-level-cache = <&L2_0>;

			};



			L2_0: l2-cache {

				compatible = "arm,arch-cache";

			};

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0x1>;

			next-level-cache = <&L1_1>;



			L1_1: l1-cache {

				compatible = "arm,arch-cache";

				next-level-cache = <&L2_0>;

			};

		};



		cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0x2>;

			next-level-cache = <&L1_2>;



			L1_2: l1-cache {

				compatible = "arm,arch-cache";

				next-level-cache = <&L2_0>;

			};

		};



		cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0x3>;

			next-level-cache = <&L1_3>;



			L1_3: l1-cache {

				compatible = "arm,arch-cache";

				next-level-cache = <&L2_0>;

			};

		};



		cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x100>;

			next-level-cache = <&L1_4>;



			L1_4: l1-cache {

				compatible = "arm,arch-cache";

				next-level-cache = <&L2_1>;

			};



			L2_1: l2-cache {

				compatible = "arm,arch-cache";

			};

		};



		cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x101>;

			next-level-cache = <&L1_5>;



			L1_5: l1-cache {

				compatible = "arm,arch-cache";

				next-level-cache = <&L2_1>;

			};

		};



		cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x102>;

			next-level-cache = <&L1_6>;



			L1_6: l1-cache {

				compatible = "arm,arch-cache";

				next-level-cache = <&L2_1>;

			};

		};



		cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0x103>;

			next-level-cache = <&L1_7>;



			L1_7: l1-cache {

				compatible = "arm,arch-cache";

				next-level-cache = <&L2_1>;

			};

		};

	};



[1] ARMv7-AR Reference Manual

    http://infocenter.arm.com/help/index.jsp

[2] ARMv8-A Reference Manual

    http://infocenter.arm.com/help/index.jsp

[3] ePAPR standard

    https://www.power.org/documentation/epapr-version-1-1/

[4] Kernel documentation - resource property bindings

    Documentation/devicetree/bindings/resource-names.txt

[5] Kernel documentation - power domain bindings

    Documentation/devicetree/bindings/power/power_domain.txt

Documentation/kernel-parameters.txt

+4 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ parameter is applicable: 
	BLACKFIN Blackfin architecture is enabled.

	CLK	Common clock infrastructure is enabled.

	CMA	Contiguous Memory Area support is enabled.

	DM	Device mapper support is enabled.

	DRM	Direct Rendering Management support is enabled.

	DYNAMIC_DEBUG Build in debug messages and enable them at runtime

	EDD	BIOS Enhanced Disk Drive Services (EDD) is enabled
@@ -919,6 +920,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 


	dis_ucode_ldr	[X86] Disable the microcode loader.



	dm=		[DM] Allows early creation of a device-mapper device.

			See Documentation/device-mapper/boot.txt.



	dma_debug=off	If the kernel is compiled with DMA_API_DEBUG support,

			this option disables the debugging code at boot.

arch/arm/boot/dts/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_MSMCOBALT) += msmcobalt-sim.dtb \ 
	msmcobalt-v2-cdp.dtb \

	msmcobalt-v2-qrd.dtb \

	msmcobalt-qrd-skuk.dtb \

	msmcobalt-v2-qrd-skuk.dtb \

	msmcobalt-qrd-vr1.dtb \

	msmcobalt-v2-qrd-vr1.dtb \

	apqcobalt-mtp.dtb \

arch/arm/boot/dts/qcom/msm8996-ion.dtsi

+1 −6
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -21,11 +21,6 @@ 
			qcom,ion-heap-type = "SYSTEM";

		};



		system_contig_heap: qcom,ion-heap@21 {

			reg = <21>;

			qcom,ion-heap-type = "SYSTEM_CONTIG";

		};



		qcom,ion-heap@22 { /* ADSP HEAP */

			reg = <22>;

			memory-region = <&adsp_mem>;