msm: pcie: Use SVS freq for pipe clock



PCIe HW supports Gen1 speed when pipe clock is set to SVS freq.
Thus, change the pipe clock freq to SVS freq which meets both
power saving and throughput requirements.

Change-Id: Ic426e06c45fde779c161ed6ccacc4fa57ccb280a
Signed-off-by: Yan He <yanhe@codeaurora.org>

parent 29011e49

arch/arm/mach-msm/pcie.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -162,10 +162,10 @@ static struct msm_pcie_clk_info_t
		static struct msm_pcie_clk_info_t
		msm_pcie_pipe_clk_info[MAX_RC_NUM][MSM_PCIE_MAX_PIPE_CLK] = {
		{
		{NULL, "pcie_0_pipe_clk", 250000000, true},
		{NULL, "pcie_0_pipe_clk", 125000000, true},
		},
		{
		{NULL, "pcie_1_pipe_clk", 250000000, true},
		{NULL, "pcie_1_pipe_clk", 125000000, true},
		}
		};