Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 29011e49 authored by Tianyi Gou's avatar Tianyi Gou Committed by Yan He
Browse files

msm: clock-8084: Configure the pcie pipe clock predivider to 1



gcc_pcie_pipe_clk frequency scaling only depends on the scaling of
its source clock. Therefore, configure the rcg predivider to 1.

Change-Id: I55d4fbb9354aeb90092e4dfe024c91a55e826486
Signed-off-by: default avatarTianyi Gou <tgou@codeaurora.org>
parent 65926263
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -1598,7 +1598,7 @@ static struct rcg_clk pcie_0_aux_clk_src = {
};

static struct clk_freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = {
	F_EXT(125000000, pcie_pipe,    2, 0, 0),
	F_EXT(125000000, pcie_pipe,    1, 0, 0),
	F_EXT(250000000, pcie_pipe,    1, 0, 0),
	F_END
};