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Commit fe9ba1a0 authored by Shrenuj Bansal's avatar Shrenuj Bansal
Browse files

msm: kgsl: Change register bit values from BIT macro to hex value 



The BIT() macro results in value being 64 bit wide. We assign the
register bit values to a 32 bit variable which results in
compilation errors. Therefore, change the value to hex to ensure
this works.

Change-Id: I05aa50adaf709d1d41877d918edf5e2d9b335830
Signed-off-by: default avatarShrenuj Bansal <shrenujb@codeaurora.org>
parent adee8411

drivers/gpu/msm/a3xx_reg.h

+11 −11
Original line number Diff line number Diff line
@@ -545,13 +545,13 @@ 
#define A3XX_VBIF_DDR_OUTPUT_RECOVERABLE_HALT_CTRL1 0x3801



/* Bit flags for RBBM_CTL */

#define RBBM_RBBM_CTL_RESET_PWR_CTR0  BIT(0)

#define RBBM_RBBM_CTL_RESET_PWR_CTR1  BIT(1)

#define RBBM_RBBM_CTL_ENABLE_PWR_CTR0  BIT(16)

#define RBBM_RBBM_CTL_ENABLE_PWR_CTR1  BIT(17)

#define RBBM_RBBM_CTL_RESET_PWR_CTR0	0x00000001

#define RBBM_RBBM_CTL_RESET_PWR_CTR1	0x00000002

#define RBBM_RBBM_CTL_ENABLE_PWR_CTR0	0x00010000

#define RBBM_RBBM_CTL_ENABLE_PWR_CTR1	0x00020000



/* Bit flag for RBMM_PERFCTR_CTL */

#define RBBM_PERFCTR_CTL_ENABLE BIT(0)

#define RBBM_PERFCTR_CTL_ENABLE		0x00000001



/* Various flags used by the context switch code */
@@ -839,11 +839,11 @@ 
#define TSE_INPUT_PRIM_NUM             0x0



/* VBIF PERFCOUNTER ENA/CLR values */

#define VBIF_PERF_CNT_0 BIT(0)

#define VBIF_PERF_CNT_1 BIT(1)

#define VBIF_PERF_PWR_CNT_0 BIT(2)

#define VBIF_PERF_PWR_CNT_1 BIT(3)

#define VBIF_PERF_PWR_CNT_2 BIT(4)

#define VBIF_PERF_CNT_0		0x00000001

#define VBIF_PERF_CNT_1		0x00000002

#define VBIF_PERF_PWR_CNT_0	0x00000004

#define VBIF_PERF_PWR_CNT_1	0x00000008

#define VBIF_PERF_PWR_CNT_2	0x00000010



/* VBIF PERFCOUNTER SEL values */

#define VBIF_PERF_CNT_0_SEL 0
@@ -856,7 +856,7 @@ 
#define VBIF_DDR_TOTAL_CYCLES 110



/* VBIF Recoverable HALT bit value */

#define VBIF_RECOVERABLE_HALT_CTRL BIT(0)

#define VBIF_RECOVERABLE_HALT_CTRL 0x1



/*

 * CP DEBUG settings for A3XX core:

drivers/gpu/msm/a4xx_reg.h

+5 −5
Original line number Diff line number Diff line 
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -612,10 +612,10 @@ enum a4xx_vfd_perfctr_vfd_sel { 
#define A4XX_VBIF_PERF_PWR_HIGH_REG_LOW_OFF	8



/* Bit flags for RBBM_CTL */

#define A4XX_RBBM_RBBM_CTL_RESET_PWR_CTR0  BIT(0)

#define A4XX_RBBM_RBBM_CTL_RESET_PWR_CTR1  BIT(1)

#define A4XX_RBBM_RBBM_CTL_ENABLE_PWR_CTR0  BIT(4)

#define A4XX_RBBM_RBBM_CTL_ENABLE_PWR_CTR1  BIT(5)

#define A4XX_RBBM_RBBM_CTL_RESET_PWR_CTR0	0x00000001

#define A4XX_RBBM_RBBM_CTL_RESET_PWR_CTR1	0x00000002

#define A4XX_RBBM_RBBM_CTL_ENABLE_PWR_CTR0	0x00000010

#define A4XX_RBBM_RBBM_CTL_ENABLE_PWR_CTR1	0x00000020



/* GRAS registers */

#define A4XX_GRAS_PERFCTR_TSE_SEL_0	0xc88