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Commit fe508d77 authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
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ARM: tegra30: common: enable csite clock 



Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gating low power state.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent d457ef35

arch/arm/mach-tegra/common.c

+1 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { 
	{ "sclk",	"pll_p_out4",	102000000,	true },

	{ "hclk",	"sclk",		102000000,	true },

	{ "pclk",	"hclk",		51000000,	true },

	{ "csite",	NULL,		0,		true },

	{ NULL,		NULL,		0,		0},

};

#endif