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Commit d457ef35 authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
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ARM: tegra30: cpuidle: add powered-down state for secondary CPUs 



This supports power-gated idle on secondary CPUs for Tegra30. The
secondary CPUs can go into powered-down state independently. When
CPU goes into this state, it saves it's contexts and puts itself
to flow controlled WFI state. After that, it will been power gated.

Be aware of that, you may see the legacy power state "LP2" in the
code which is exactly the same meaning of "CPU power down".

Based on the work by:
Scott Williams <scwilliams@nvidia.com>

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent d3f29365

arch/arm/mach-tegra/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ obj-y += pmc.o 
obj-y					+= flowctrl.o

obj-y					+= powergate.o

obj-y					+= apbio.o

obj-y					+= pm.o

obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o

obj-$(CONFIG_CPU_IDLE)			+= sleep.o

obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o

arch/arm/mach-tegra/cpuidle-tegra30.c

+86 −0
Original line number Diff line number Diff line
@@ -22,21 +22,107 @@ 
#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/cpuidle.h>

#include <linux/cpu_pm.h>

#include <linux/clockchips.h>



#include <asm/cpuidle.h>

#include <asm/proc-fns.h>

#include <asm/suspend.h>

#include <asm/smp_plat.h>



#include "pm.h"

#include "sleep.h"



#ifdef CONFIG_PM_SLEEP

static int tegra30_idle_lp2(struct cpuidle_device *dev,

			    struct cpuidle_driver *drv,

			    int index);

#endif



static struct cpuidle_driver tegra_idle_driver = {

	.name = "tegra_idle",

	.owner = THIS_MODULE,

	.en_core_tk_irqen = 1,

#ifdef CONFIG_PM_SLEEP

	.state_count = 2,

#else

	.state_count = 1,

#endif

	.states = {

		[0] = ARM_CPUIDLE_WFI_STATE_PWR(600),

#ifdef CONFIG_PM_SLEEP

		[1] = {

			.enter			= tegra30_idle_lp2,

			.exit_latency		= 2000,

			.target_residency	= 2200,

			.power_usage		= 0,

			.flags			= CPUIDLE_FLAG_TIME_VALID,

			.name			= "powered-down",

			.desc			= "CPU power gated",

		},

#endif

	},

};



static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);



#ifdef CONFIG_PM_SLEEP

#ifdef CONFIG_SMP

static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,

					struct cpuidle_driver *drv,

					int index)

{

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);



	smp_wmb();



	save_cpu_arch_register();



	cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);



	restore_cpu_arch_register();



	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);



	return true;

}

#else

static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,

					       struct cpuidle_driver *drv,

					       int index)

{

	return true;

}

#endif



static int __cpuinit tegra30_idle_lp2(struct cpuidle_device *dev,

				      struct cpuidle_driver *drv,

				      int index)

{

	u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;

	bool entered_lp2 = false;



	local_fiq_disable();



	tegra_set_cpu_in_lp2(cpu);

	cpu_pm_enter();



	if (cpu == 0)

		cpu_do_idle();

	else

		entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);



	cpu_pm_exit();

	tegra_clear_cpu_in_lp2(cpu);



	local_fiq_enable();



	smp_rmb();



	return (entered_lp2) ? index : 0;

}

#endif



int __init tegra30_cpuidle_init(void)

{

	int ret;

arch/arm/mach-tegra/pm.c

0 → 100644
+74 −0
Original line number Diff line number Diff line 
/*

 * CPU complex suspend & resume functions for Tegra SoCs

 *

 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include <linux/kernel.h>

#include <linux/spinlock.h>

#include <linux/io.h>

#include <linux/cpumask.h>



#include "iomap.h"

#include "reset.h"



#ifdef CONFIG_PM_SLEEP

static unsigned int g_diag_reg;

static DEFINE_SPINLOCK(tegra_lp2_lock);



void save_cpu_arch_register(void)

{

	/* read diagnostic register */

	asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");

	return;

}



void restore_cpu_arch_register(void)

{

	/* write diagnostic register */

	asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");

	return;

}



void __cpuinit tegra_clear_cpu_in_lp2(int phy_cpu_id)

{

	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;



	spin_lock(&tegra_lp2_lock);



	BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));

	*cpu_in_lp2 &= ~BIT(phy_cpu_id);



	spin_unlock(&tegra_lp2_lock);

}



bool __cpuinit tegra_set_cpu_in_lp2(int phy_cpu_id)

{

	bool last_cpu = false;

	cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;

	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;



	spin_lock(&tegra_lp2_lock);



	BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));

	*cpu_in_lp2 |= BIT(phy_cpu_id);



	if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))

		last_cpu = true;



	spin_unlock(&tegra_lp2_lock);

	return last_cpu;

}

#endif

arch/arm/mach-tegra/pm.h

0 → 100644
+30 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2010 Google, Inc.

 * Copyright (c) 2010-2012 NVIDIA Corporation. All rights reserved.

 *

 * Author:

 *	Colin Cross <ccross@google.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef _MACH_TEGRA_PM_H_

#define _MACH_TEGRA_PM_H_



void save_cpu_arch_register(void);

void restore_cpu_arch_register(void);



void tegra_clear_cpu_in_lp2(int phy_cpu_id);

bool tegra_set_cpu_in_lp2(int phy_cpu_id);



#endif /* _MACH_TEGRA_PM_H_ */

arch/arm/mach-tegra/reset.h

+9 −0
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 


#ifndef __ASSEMBLY__



#include "irammap.h"



extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];



void __tegra_cpu_reset_handler_start(void);
@@ -36,6 +38,13 @@ void __tegra_cpu_reset_handler(void); 
void __tegra_cpu_reset_handler_end(void);

void tegra_secondary_startup(void);



#ifdef CONFIG_PM_SLEEP

#define tegra_cpu_lp2_mask \

	(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \

	((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \

	 (u32)__tegra_cpu_reset_handler_start)))

#endif



#define tegra_cpu_reset_handler_offset \

		((u32)__tegra_cpu_reset_handler - \

		 (u32)__tegra_cpu_reset_handler_start)