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Commit fd0a2706 authored by Vikram Mulukutla's avatar Vikram Mulukutla
Browse files

clk: qcom: clock-cpu-8994: Fix PLL rate refusal window during boot 



The PLL ping-pong scheme is implemented by having the
PLL reject a round_rate request when it is prepared.
During boot, there may be a small window where both PLLs
are prepared, and this neither PLL will satisfy a
round_rate request. Fix this by ensuring both PLLs are
off in early_init. We're switching to the GPLL0 source
anyway, so there's no harm in turning off the CPU PLLs.

Change-Id: I7d4bd60bdbfb1b8687e76be55dee373742d1a1f2
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent e064da89

drivers/clk/qcom/clock-cpu-8994.c

+21 −1
Original line number Diff line number Diff line
@@ -2202,12 +2202,32 @@ int __init cpu_clock_8994_init_a57_v2(void) 
	/* Select GPLL0 for 600MHz on the A53s */

	writel_relaxed(0x6, vbases[ALIAS0_GLB_BASE] + MUX_OFFSET);



	/* Ensure write goes through before we disable PLLs below. */

	mb();

	udelay(5);



	/*

	 * Disable the PLLs in order to allow early rate setting to work.

	 * The PLL ping-pong scheme needs the PLL to refuse round_rate

	 * requests if prepare. However handoff will set the PLL ref count

	 * to one thus preventing PLL ping-ponging to work correctly before

	 * late_init.

	 */

	writel_relaxed(0x0,  vbases[C0_PLL_BASE] + C0_PLL_MODE);

	writel_relaxed(0x0,  vbases[C0_PLL_BASE] + C0_PLLA_MODE);

	writel_relaxed(0x0,  vbases[C1_PLL_BASE] + C1_PLL_MODE);

	writel_relaxed(0x0,  vbases[C1_PLL_BASE] + C1_PLLA_MODE);



	/* Ensure writes go through before divider config below */

	mb();

	udelay(5);



	/* Setup dividers and outputs */

	writel_relaxed(0x109, vbases[C0_PLL_BASE] + C0_PLLA_USER_CTL);

	writel_relaxed(0x109, vbases[C1_PLL_BASE] + C1_PLL_USER_CTL);

	writel_relaxed(0x109, vbases[C1_PLL_BASE] + C1_PLLA_USER_CTL);



	/* Ensure write goes through before A53s are brought up. */

	/* Ensure writes go through before clock driver probe */

	mb();

	udelay(5);