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Commit fa6d1e8f authored by Hanumath Prasad's avatar Hanumath Prasad Committed by Anirudh Ghayal
Browse files

clock: cpu: Add support for 1.113 GHz to power cluster



Add support upto 1.113 GHz for power cluster and update the
corresponding virtual corner value to 26/24 for speed-bin 4/5.
Update the clk driver frequency table power cluster PLL with
the corresponding frequencies.

Change-Id: Ia3e5deb9318b14ea58fa1acea1046629d50fdf0A
Signed-off-by: default avatarHanumath Prasad <hpprasad@codeaurora.org>
Signed-off-by: default avatarFenglin Wu <fenglinw@codeaurora.org>
parent 1add83af
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+14 −7
Original line number Diff line number Diff line
@@ -65,7 +65,8 @@
			<  250000000 3>,
			<  500000000 9>,
			<  800000000 12>,
			<  998400000 17>;
			<  998400000 17>,
			< 1113600000 22>;

		qcom,speed0-bin-v0-c1 =
			<          0 0>,
@@ -92,7 +93,8 @@
			<  250000000 3>,
			<  500000000 9>,
			<  800000000 12>,
			<  998400000 17>;
			<  998400000 17>,
			< 1113600000 22>;

		qcom,speed2-bin-v0-c1 =
			<          0 0>,
@@ -121,7 +123,8 @@
			<  250000000 3>,
			<  500000000 9>,
			<  800000000 12>,
			<  998400000 17>;
			<  998400000 17>,
			< 1113600000 26>;

		qcom,speed4-bin-v0-c1 =
			<          0 0>,
@@ -155,7 +158,8 @@
			<  250000000 3>,
			<  500000000 9>,
			<  800000000 12>,
			<  998400000 17>;
			<  998400000 17>,
			< 1113600000 24>;

		qcom,speed5-bin-v0-c1 =
			<          0 0>,
@@ -246,7 +250,8 @@
			<  499200 2526 >,
			<  533330 2526 >,
			<  800000 5053 >,
			<  998400 6079 >;
			<  998400 6079 >,
			< 1113600 6079 >;
		};

		cci-cpufreq {
@@ -283,7 +288,8 @@
			<  499200 297600 >,
			<  533330 297600 >,
			<  800000 297600 >,
			<  998400 595200 >;
			<  998400 595200 >,
			< 1113600 595200 >;
		};
	};

@@ -336,7 +342,8 @@
			 <  499200 >,
			 <  533330 >,
			 <  800000 >,
			 <  998400 >;
			 <  998400 >,
			 < 1113600 >;
	};

	cpu-pmu {
+2 −1
Original line number Diff line number Diff line
@@ -465,6 +465,7 @@ static struct pll_clk a53ss_cci_pll = {

static struct pll_freq_tbl apcs_c0_pll_freq[] = {
	F_APCS_PLL( 998400000,  52, 0x0, 0x1, 0x0, 0x0, 0x0),
	F_APCS_PLL(1113600000,  58, 0x0, 0x1, 0x0, 0x0, 0x0),
};

static struct pll_clk a53ss_c0_pll = {