Loading arch/arm/boot/dts/qcom/msm8939-pinctrl.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -208,6 +208,23 @@ }; }; pmx_i2c_5 { qcom,pins = <&gp 18>, <&gp 19>; /* SDA, SCL */ qcom,num-grp-pins = <2>; qcom,pin-func = <2>; label = "pmx_i2c_5"; i2c_5_active: i2c_5_active { drive-strength = <2>; bias-disable; }; i2c_5_sleep: i2c_5_sleep { drive-strength = <2>; bias-disable; }; }; smb_int_pin { qcom,pins = <&gp 62>; qcom,num-grp-pins = <1>; Loading arch/arm/boot/dts/qcom/msm8939.dtsi +27 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ smd36 = &smdtty_loopback; i2c0 = &i2c_0; i2c4 = &i2c_4; i2c5 = &i2c_5; spi0 = &spi_0; }; Loading Loading @@ -1122,6 +1123,32 @@ qcom,master-id = <86>; }; i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78b9000 0x600>, <0x7884000 0x23000>; interrupt-names = "qup_irq", "bam_irq"; interrupts = <0 99 0>, <0 238 0>; qcom,clk-freq-out = <100000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_5_active>; pinctrl-1 = <&i2c_5_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,bam-pipe-idx-cons = <12>; qcom,bam-pipe-idx-prod = <13>; qcom,master-id = <86>; }; spmi_bus: qcom,spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, Loading Loading
arch/arm/boot/dts/qcom/msm8939-pinctrl.dtsi +17 −0 Original line number Diff line number Diff line Loading @@ -208,6 +208,23 @@ }; }; pmx_i2c_5 { qcom,pins = <&gp 18>, <&gp 19>; /* SDA, SCL */ qcom,num-grp-pins = <2>; qcom,pin-func = <2>; label = "pmx_i2c_5"; i2c_5_active: i2c_5_active { drive-strength = <2>; bias-disable; }; i2c_5_sleep: i2c_5_sleep { drive-strength = <2>; bias-disable; }; }; smb_int_pin { qcom,pins = <&gp 62>; qcom,num-grp-pins = <1>; Loading
arch/arm/boot/dts/qcom/msm8939.dtsi +27 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ smd36 = &smdtty_loopback; i2c0 = &i2c_0; i2c4 = &i2c_4; i2c5 = &i2c_5; spi0 = &spi_0; }; Loading Loading @@ -1122,6 +1123,32 @@ qcom,master-id = <86>; }; i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */ compatible = "qcom,i2c-msm-v2"; #address-cells = <1>; #size-cells = <0>; reg-names = "qup_phys_addr", "bam_phys_addr"; reg = <0x78b9000 0x600>, <0x7884000 0x23000>; interrupt-names = "qup_irq", "bam_irq"; interrupts = <0 99 0>, <0 238 0>; qcom,clk-freq-out = <100000>; qcom,clk-freq-in = <19200000>; clock-names = "iface_clk", "core_clk"; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>; pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_5_active>; pinctrl-1 = <&i2c_5_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,bam-pipe-idx-cons = <12>; qcom,bam-pipe-idx-prod = <13>; qcom,master-id = <86>; }; spmi_bus: qcom,spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x200f000 0x1000>, Loading