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Commit ed08b518 authored by Deepak Katragadda's avatar Deepak Katragadda
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msm: subsys-pil-tz: Move VPU PIL/SSR support to generic PIL/SSR driver 



The need for a seperate VPU PIL/SSR driver goes away by leveraging
the functionality of the generic PIL/SSR driver.

Change-Id: I71bd5231b25e1b16786bba0ca36d0f5304732198
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 1e9cff42

Documentation/devicetree/bindings/pil/pil-vpu.txt

deleted100644 → 0
+0 −28
Original line number Diff line number Diff line 
* Qualcomm Video Processing Unit Subsystem Peripheral Image Loader



pil-vpu is a peripheral image loading (PIL) driver. It is used for loading

vpu firmware images for video processing into memory and preparing the subsystem's

processor to execute code. It is also used for shutting down the processor when

it's not needed.



Required properties:

- compatible: "pil-vpu"

- reg: offset and length of the register set for the device.

- reg-names: names of the bases for the above registers. "maple_csr_base".

- vdd-supply: regulator to supply vpu.

- qcom,firmware-name: Base name of the firmware image. Ex. "vpu"



Optional properties:

- qcom,restart-group: List of subsystems that will need to restart together.



Example:



	qcom,vpu@fde0b000{

		compatible = "qcom,pil-vpu";

		reg = <0xfde0b000 0x80>;

		reg-names = "maple_csr_base";

		vdd-supply = <&gdsc_vpu>;



		qcom,firmware-name = "vpu";

	};

arch/arm/boot/dts/qcom/apq8084.dtsi

+13 −5
Original line number Diff line number Diff line
@@ -3471,13 +3471,21 @@ 
	};



	qcom,pil-vpu@fde0b000{

		compatible = "qcom,pil-vpu";

		compatible = "qcom,pil-tz-generic";

		reg = <0xfde0b000 0x80>;

		reg-names = "maple_csr_base";

		vdd-supply = <&gdsc_vpu>;

		clock-names = "core_clk", "iface_clk", "bus_clk", "vdp_clk",

					"vdp_bus_clk", "cxo_clk", "sleep_clk", "maple_bus_clk";



		vdd-supply = <&gdsc_vpu>;

		proxy-reg-names = "vdd";

		active-reg-names = "vdd";

		clock-names = "core_clk", "iface_clk", "bus_clk",

				"vdp_clk", "vdp_bus_clk", "cxo_clk",

				"sleep_clk", "maple_bus_clk";

		proxy-clock-names = "core_clk", "iface_clk", "bus_clk",

					"vdp_clk", "vdp_bus_clk", "cxo_clk",

					"sleep_clk", "maple_bus_clk";



		qcom,pas-id = <10>;

		qcom,proxy-timeout-ms = <10000>;

		qcom,firmware-name = "vpu";

	};

arch/arm/boot/dts/qcom/mpq8092.dtsi

+8 −3
Original line number Diff line number Diff line
@@ -1070,13 +1070,18 @@ 
	};



	qcom,pil-vpu@fde0b000 {

		compatible = "qcom,pil-vpu";

		compatible = "qcom,pil-tz-generic";

		reg = <0xfde0b000 0x80>;

		reg-names = "maple_csr_base";



		vdd-supply = <&gdsc_vpu>;

		proxy-reg-names = "vdd";

		active-reg-names = "vdd";

		clock-names = "core_clk", "iface_clk", "bus_clk", "vdp_clk",

					"vdp_bus_clk", "sleep_clk", "maple_bus_clk";



		proxy-clock-names = "core_clk", "iface_clk", "bus_clk", "vdp_clk",

					"vdp_bus_clk", "sleep_clk", "maple_bus_clk";

		qcom,pas-id = <10>;

		qcom,proxy-timeout-ms = <10000>;

		qcom,firmware-name = "vpu";

	};

arch/arm/configs/apq8084-perf_defconfig

+0 −1
Original line number Diff line number Diff line
@@ -50,7 +50,6 @@ CONFIG_MSM_SUBSYSTEM_RESTART=y 
CONFIG_MSM_SYSMON_COMM=y

CONFIG_MSM_PIL_SSR_GENERIC=y

CONFIG_MSM_PIL_LPASS_QDSP6V5=y

CONFIG_MSM_PIL_VPU=y

CONFIG_MSM_BUSPM_DEV=m

CONFIG_MSM_TZ_LOG=y

CONFIG_MSM_DIRECT_SCLK_ACCESS=y

arch/arm/configs/apq8084_defconfig

+0 −1
Original line number Diff line number Diff line
@@ -49,7 +49,6 @@ CONFIG_MSM_SUBSYSTEM_RESTART=y 
CONFIG_MSM_SYSMON_COMM=y

CONFIG_MSM_PIL_SSR_GENERIC=y

CONFIG_MSM_PIL_LPASS_QDSP6V5=y

CONFIG_MSM_PIL_VPU=y

CONFIG_MSM_BUSPM_DEV=m

CONFIG_MSM_TZ_LOG=y

CONFIG_MSM_DIRECT_SCLK_ACCESS=y