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Commit ecbb0659 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Paul Walmsley
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OMAP4: clocks: Fix the clksel_rate struct DPLL divs



For all DPLL's the valid dividers are same as the values
to be programmed in the register. 0 is an invalid value.
The changes are generated by updating the script which autogenerates
the file modifed in the patch.

Signed-off-by: default avatarRajendra Nayak <rnayak@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 0324f59f
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