ARM: dts: msm: Update minbw table for MSM8994 v2 to improve performance

This update ensures that there is no performance degradation due to the
bus/DDR running slow when there is at least a single threaded workload
that's keeps the CPU completely busy but has sporadic low bandwidth memory
access due to infrequent cache misses.

Change-Id: I66f7ac0889e953144a3679fffda31145310445e8
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>