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Commit e61e87e4 authored by Michael Bohan's avatar Michael Bohan
Browse files

Merge branch '8916-dev-phase2' into msm-3.10. 



Merge the second phase of support needed for the 8916
target into msm-3.10. This includes a couple hundred upstream
patches for ARM64 support, as well as 8916 specific driver
development.

* origin/tmp-branch: (211 commits)
  ARM: dts: msmplutonium: Update the cpu release address
  Revert "arm64: Fix memory shareability attribute for ioremap_wc/cache"
  clocksource: arch_timer: Do not register arch_sys_counter twice
  xtensa: adjust boot parameters address when INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX is selected
  sched_clock: Add support for >32 bit sched_clock
  sched_clock: Use an hrtimer instead of timer
  sched_clock: Use seqcount instead of rolling our own
  clocksource: Extract max nsec calculation into separate function
  ARM: sched_clock: Load cycle count after epoch stabilizes
  sched_clock: Make ARM's sched_clock generic for all architectures
  of: move of_get_cpu_node implementation to DT core library
  of: introduce common FDT machine related functions
  of: Introduce common early_init_dt_scan
  mm: allow pgtable_page_ctor() to fail
  of: only include prom.h on sparc
  mm: introduce helper function mem_init_print_info() to simplify mem_init()
  mm: use a dedicated lock to protect totalram_pages and zone->managed_pages
  KVM: Move gfn_to_index to x86 specific code
  ARM: KVM: move GIC/timer code to a common location
  arm64: mm: Fix PMD_SECT_PROT_NONE definition
  ...

Conflicts:
	arch/arm/mach-msm/board-8226.c
	arch/arm/mach-msm/board-8610.c
	arch/arm64/kernel/asm-offsets.c
	arch/arm64/kernel/fpsimd.c
	arch/arm64/kernel/setup.c

Change-Id: I289996bc18d8a2782906e7db1171b48e3ee46a73
Signed-off-by: default avatarMichael Bohan <mbohan@codeaurora.org>
parents af289785 490a09a5

Documentation/arm64/booting.txt

+13 −3
Original line number Diff line number Diff line
@@ -68,13 +68,23 @@ Image target is available instead. 


Requirement: MANDATORY



The decompressed kernel image contains a 32-byte header as follows:

The decompressed kernel image contains a 64-byte header as follows:



  u32 magic	= 0x14000008;	/* branch to stext, little-endian */

  u32 res0	= 0;		/* reserved */

  u32 code0;			/* Executable code */

  u32 code1;			/* Executable code */

  u64 text_offset;		/* Image load offset */

  u64 res0	= 0;		/* reserved */

  u64 res1	= 0;		/* reserved */

  u64 res2	= 0;		/* reserved */

  u64 res3	= 0;		/* reserved */

  u64 res4	= 0;		/* reserved */

  u32 magic	= 0x644d5241;	/* Magic number, little endian, "ARM\x64" */

  u32 res5 = 0;      		/* reserved */





Header notes:



- code0/code1 are responsible for branching to stext.



The image must be placed at the specified offset (currently 0x80000)

from the start of the system RAM and called there. The start of the

Documentation/arm64/memory.txt

+26 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ The swapper_pgd_dir address is written to TTBR1 and never written to 
TTBR0.





AArch64 Linux memory layout:

AArch64 Linux memory layout with 4KB pages:



Start			End			Size		Use

-----------------------------------------------------------------------
@@ -46,6 +46,31 @@ ffffffbffc000000 ffffffbfffffffff 64MB modules 
ffffffc000000000	ffffffffffffffff	 256GB		kernel logical memory map





AArch64 Linux memory layout with 64KB pages:



Start			End			Size		Use

-----------------------------------------------------------------------

0000000000000000	000003ffffffffff	   4TB		user



fffffc0000000000	fffffdfbfffeffff	  ~2TB		vmalloc



fffffdfbffff0000	fffffdfbffffffff	  64KB		[guard page]



fffffdfc00000000	fffffdfdffffffff	   8GB		vmemmap



fffffdfe00000000	fffffdfffbbfffff	  ~8GB		[guard, future vmmemap]



fffffdfffbc00000	fffffdfffbdfffff	   2MB		earlyprintk device



fffffdfffbe00000	fffffdfffbe0ffff	  64KB		PCI I/O space



fffffdfffbe10000	fffffdfffbffffff	  ~2MB		[guard]



fffffdfffc000000	fffffdffffffffff	  64MB		modules



fffffe0000000000	ffffffffffffffff	   2TB		kernel logical memory map





Translation table lookup with 4KB pages:



+--------+--------+--------+--------+--------+--------+--------+--------+

Documentation/arm64/tagged-pointers.txt

0 → 100644
+34 −0
Original line number Diff line number Diff line 
		Tagged virtual addresses in AArch64 Linux

		=========================================



Author: Will Deacon <will.deacon@arm.com>

Date  : 12 June 2013



This document briefly describes the provision of tagged virtual

addresses in the AArch64 translation system and their potential uses

in AArch64 Linux.



The kernel configures the translation tables so that translations made

via TTBR0 (i.e. userspace mappings) have the top byte (bits 63:56) of

the virtual address ignored by the translation hardware. This frees up

this byte for application use, with the following caveats:



	(1) The kernel requires that all user addresses passed to EL1

	    are tagged with tag 0x00. This means that any syscall

	    parameters containing user virtual addresses *must* have

	    their top byte cleared before trapping to the kernel.



	(2) Tags are not guaranteed to be preserved when delivering

	    signals. This means that signal handlers in applications

	    making use of tags cannot rely on the tag information for

	    user virtual addresses being maintained for fields inside

	    siginfo_t. One exception to this rule is for signals raised

	    in response to debug exceptions, where the tag information

	    will be preserved.



	(3) Special care should be taken when using tagged pointers,

	    since it is likely that C compilers will not hazard two

	    addresses differing only in the upper bits.



The architecture prevents the use of a tagged PC, so the upper byte will

be set to a sign-extension of bit 55 on exception return.

Documentation/devicetree/bindings/arm/msm/msm_thermal.txt

+21 −0
Original line number Diff line number Diff line
@@ -90,6 +90,27 @@ Optional properties 
			phandle_of_regulator is defined by reuglator device tree.



Optional child nodes

- qcom,pmic-opt-curr-temp: Threshold temperature for requesting optimum current (request

			dual phase) for rails with PMIC, in degC. If this property exists,

			then the properties, qcom,pmic-opt-curr-temp-hysteresis and

			qcom,pmic-opt-curr-regs should also be defined to enable this

			feature.

- qcom,pmic-opt-curr-temp-hysteresis: Degree below the threshold to disable the optimum

			current request for a rail, in degC. If this property exists,

			then the properties, qcom,pmic-opt-curr-temp and

			qcom,pmic-opt-curr-regs should also be defined to enable

			this feature.

- qcom,pmic-opt-curr-regs: Name of the rails for which the optimum current should be

			requested. If this property exists, then the properties,

			qcom,pmic-opt-curr-temp and qcom,pmic-opt-curr-temp-hysteresis

			should also be defined to enable this feature.

- qcom,pmic-opt-curr-sensor-id: Sensor, which needs to be monitored for requesting OCR

			when qcom,pmic-opt-curr-temp threshold is reached.

			It is an optional property, if it is configured, msm_thermal will

			monitor only this sensor, otherwise it will monitor all TSENS for

			this feature. If this property exists, then the properties,

			qcom,pmic-opt-curr-temp, qcom,pmic-opt-curr-temp-hysteresis and

			qcom,pmic-opt-curr-regs should also be defined to enable this feature.

- qcom,<vdd restriction child node name>: Define the name of the child node.

			If this property exisits, qcom,vdd-rstr-reg, qcom,levels

			need to exist. qcom,min-level is optional if qcom,freq-req

arch/Kconfig

+0 −3
Original line number Diff line number Diff line
@@ -207,9 +207,6 @@ config HAVE_DMA_ATTRS 
config HAVE_DMA_CONTIGUOUS

	bool



config USE_GENERIC_SMP_HELPERS

	bool



config GENERIC_SMP_IDLE_THREAD

       bool