Loading Documentation/devicetree/bindings/usb/msm-phy.txt +2 −0 Original line number Diff line number Diff line Loading @@ -101,6 +101,8 @@ Optional properties: the USB PHY and the controller must rely on external VBUS notification in order to manually relay the notification to the SSPHY. - qcom,ext-vbus-id: If present, indicates that the PHY does not handle VBUS and ID changes. - qcom,no-pipe-clk-switch: If present, indicates that the pipe_clk does not need to switch sources between the XO and the PHY PIPE clock output. Example: ssphy0: ssphy@f9b38000 { Loading drivers/usb/phy/phy-msm-ssusb-qmp.c +22 −11 Original line number Diff line number Diff line Loading @@ -192,6 +192,7 @@ struct msm_ssphy_qmp { bool in_suspend; bool ext_vbus_id; bool override_pll_cal; bool switch_pipe_clk_src; }; static inline char *get_cable_status_str(struct msm_ssphy_qmp *phy) Loading Loading @@ -316,6 +317,7 @@ static int msm_ssphy_qmp_init_clocks(struct msm_ssphy_qmp *phy) goto disable_cfg_ahb_clk; } if (phy->switch_pipe_clk_src) { /* * Before PHY is initilized we must first use the xo clock * as the source clock for the gcc_usb3_pipe_clk in 19.2MHz Loading @@ -323,6 +325,7 @@ static int msm_ssphy_qmp_init_clocks(struct msm_ssphy_qmp *phy) */ clk_set_rate(phy->pipe_clk, 19200000); clk_prepare_enable(phy->pipe_clk); } /* otherwise pipe_clk must be enabled after initialization */ phy->phy_com_reset = devm_clk_get(phy->phy.dev, "phy_com_reset"); if (IS_ERR(phy->phy_com_reset)) Loading Loading @@ -411,6 +414,10 @@ static int msm_ssphy_qmp_init(struct usb_phy *uphy) writel_relaxed(0x00, phy->base + PCIE_USB3_PHY_SW_RESET); writel_relaxed(0x03, phy->base + PCIE_USB3_PHY_START); if (!phy->switch_pipe_clk_src) /* this clock wasn't enabled before, enable it now */ clk_prepare_enable(phy->pipe_clk); /* Wait for PHY initialization to be done */ do { if (readl_relaxed(phy->base + PCIE_USB3_PHY_PCS_STATUS) & Loading @@ -427,11 +434,12 @@ static int msm_ssphy_qmp_init(struct usb_phy *uphy) /* * After PHY initilization above, the PHY is generating * the usb3_pipe_clk in 125MHz. Therefore now we can (and need) * to switch the gcc_usb3_pipe_clk to 125MHz as well, so * the gcc_usb3_pipe_clk is sourced now from the usb3_pipe3_clk * the usb3_pipe_clk in 125MHz. Therefore now we can (if needed) * switch the gcc_usb3_pipe_clk to 125MHz as well, so the * gcc_usb3_pipe_clk is sourced now from the usb3_pipe3_clk * instead of from the xo clock. */ if (phy->switch_pipe_clk_src) clk_set_rate(phy->pipe_clk, 125000000); return 0; Loading Loading @@ -700,6 +708,9 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev) if (phy->override_pll_cal) dev_dbg(dev, "Override PHY PLL calibration is enabled.\n"); phy->switch_pipe_clk_src = !of_property_read_bool(dev->of_node, "qcom,no-pipe-clk-switch"); phy->phy.dev = dev; phy->phy.init = msm_ssphy_qmp_init; phy->phy.set_suspend = msm_ssphy_qmp_set_suspend; Loading Loading
Documentation/devicetree/bindings/usb/msm-phy.txt +2 −0 Original line number Diff line number Diff line Loading @@ -101,6 +101,8 @@ Optional properties: the USB PHY and the controller must rely on external VBUS notification in order to manually relay the notification to the SSPHY. - qcom,ext-vbus-id: If present, indicates that the PHY does not handle VBUS and ID changes. - qcom,no-pipe-clk-switch: If present, indicates that the pipe_clk does not need to switch sources between the XO and the PHY PIPE clock output. Example: ssphy0: ssphy@f9b38000 { Loading
drivers/usb/phy/phy-msm-ssusb-qmp.c +22 −11 Original line number Diff line number Diff line Loading @@ -192,6 +192,7 @@ struct msm_ssphy_qmp { bool in_suspend; bool ext_vbus_id; bool override_pll_cal; bool switch_pipe_clk_src; }; static inline char *get_cable_status_str(struct msm_ssphy_qmp *phy) Loading Loading @@ -316,6 +317,7 @@ static int msm_ssphy_qmp_init_clocks(struct msm_ssphy_qmp *phy) goto disable_cfg_ahb_clk; } if (phy->switch_pipe_clk_src) { /* * Before PHY is initilized we must first use the xo clock * as the source clock for the gcc_usb3_pipe_clk in 19.2MHz Loading @@ -323,6 +325,7 @@ static int msm_ssphy_qmp_init_clocks(struct msm_ssphy_qmp *phy) */ clk_set_rate(phy->pipe_clk, 19200000); clk_prepare_enable(phy->pipe_clk); } /* otherwise pipe_clk must be enabled after initialization */ phy->phy_com_reset = devm_clk_get(phy->phy.dev, "phy_com_reset"); if (IS_ERR(phy->phy_com_reset)) Loading Loading @@ -411,6 +414,10 @@ static int msm_ssphy_qmp_init(struct usb_phy *uphy) writel_relaxed(0x00, phy->base + PCIE_USB3_PHY_SW_RESET); writel_relaxed(0x03, phy->base + PCIE_USB3_PHY_START); if (!phy->switch_pipe_clk_src) /* this clock wasn't enabled before, enable it now */ clk_prepare_enable(phy->pipe_clk); /* Wait for PHY initialization to be done */ do { if (readl_relaxed(phy->base + PCIE_USB3_PHY_PCS_STATUS) & Loading @@ -427,11 +434,12 @@ static int msm_ssphy_qmp_init(struct usb_phy *uphy) /* * After PHY initilization above, the PHY is generating * the usb3_pipe_clk in 125MHz. Therefore now we can (and need) * to switch the gcc_usb3_pipe_clk to 125MHz as well, so * the gcc_usb3_pipe_clk is sourced now from the usb3_pipe3_clk * the usb3_pipe_clk in 125MHz. Therefore now we can (if needed) * switch the gcc_usb3_pipe_clk to 125MHz as well, so the * gcc_usb3_pipe_clk is sourced now from the usb3_pipe3_clk * instead of from the xo clock. */ if (phy->switch_pipe_clk_src) clk_set_rate(phy->pipe_clk, 125000000); return 0; Loading Loading @@ -700,6 +708,9 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev) if (phy->override_pll_cal) dev_dbg(dev, "Override PHY PLL calibration is enabled.\n"); phy->switch_pipe_clk_src = !of_property_read_bool(dev->of_node, "qcom,no-pipe-clk-switch"); phy->phy.dev = dev; phy->phy.init = msm_ssphy_qmp_init; phy->phy.set_suspend = msm_ssphy_qmp_set_suspend; Loading
