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Commit 876d0caf authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "usb: phy: qmp: Fix and update rev1 initialization parameters"

parents 23afe938 eda694f7

drivers/usb/phy/phy-msm-ssusb-qmp.c

+16 −11
Original line number Diff line number Diff line
@@ -33,8 +33,6 @@ 
#define PCIE_USB3_PHY_SW_RESET			0x600

#define PCIE_USB3_PHY_POWER_DOWN_CONTROL	0x604

#define PCIE_USB3_PHY_START			0x608

#define PCIE_USB3_PHY_RX_IDLE_DTCT_CNTRL	0x64C

#define PCIE_USB3_PHY_POWER_STATE_CONFIG2	0x654

#define PCIE_USB3_PHY_AUTONOMOUS_MODE_CTRL	0x6BC



#define PCIE_USB3_PHY_PCS_STATUS		0x728
@@ -120,12 +118,12 @@ static const struct qmp_reg_val qmp_settings_rev1[] = { 
	{0x10C, 0x03}, /* QSERDES_COM_DEC_START2 */

	{0x100, 0xD5}, /* QSERDES_COM_DIV_FRAC_START1 */

	{0x104, 0xAA}, /* QSERDES_COM_DIV_FRAC_START2 */

	{0x100, 0x4D}, /* QSERDES_COM_DIV_FRAC_START3 */

	{0x108, 0x4D}, /* QSERDES_COM_DIV_FRAC_START3 */

	{0x9C, 0x01}, /* QSERDES_COM_PLLLOCK_CMP_EN */

	{0x90, 0x2B}, /* QSERDES_COM_PLLLOCK_CMP1 */

	{0x94, 0x68}, /* QSERDES_COM_PLLLOCK_CMP2 */

	{0x114, 0x7C}, /* QSERDES_COM_PLL_CRCTRL */

	{0x34, 0x02}, /* QSERDES_COM_PLL_CP_SETI */

	{0x34, 0x07}, /* QSERDES_COM_PLL_CP_SETI */

	{0x38, 0x1F}, /* QSERDES_COM_PLL_IP_SETP */

	{0x3C, 0x0F}, /* QSERDES_COM_PLL_CP_SETP */

	{0x24, 0x01}, /* QSERDES_COM_PLL_IP_SETI */
@@ -134,31 +132,38 @@ static const struct qmp_reg_val qmp_settings_rev1[] = { 
	{0x14, 0x46}, /* QSERDES_COM_PLL_CNTRL */



	/* CDR Settings */

	{0x400, 0xDA}, /* QSERDES_RX_CDR_CONTROL1 */

	{0x404, 0x42}, /* QSERDES_RX_CDR_CONTROL2 */

	{0x41C, 0x75}, /* QSERDEX_RX_UCDR_SO_SATURATION_AND_ENABLE */



	/* Calibration Settings */

	{0x4C, 0x90}, /* QSERDES_COM_RESETSM_CNTRL */

	{0x50, 0x05}, /* QSERDES_COM_RESETSM_CNTRL2 */

	{0x50, 0x07}, /* QSERDES_COM_RESETSM_CNTRL2 */

	{0x04, 0xE1}, /* QSERDES_COM_PLL_VCOTAIL_EN */



	{0xE0, 0x20}, /* QSERDES_COM_RES_CODE_START_SEG1 */

	{0xE8, 0x77}, /* QSERDES_COM_RES_CODE_CAL_CSR */

	{0xF0, 0x15}, /* QSERDES_COM_RES_TRIM_CONTROL */

	{0x268, 0x03}, /* QSERDES_TX_RCV_DETECT_LVL */

	{0x4BC, 0x02}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */

	{0x268, 0x02}, /* QSERDES_TX_RCV_DETECT_LVL */

	{0x4F0, 0x67}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */

	{0x4F4, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */

	{0x4BC, 0x06}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */

	{0x4C0, 0x6C}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */

	{0x4C4, 0xC7}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */

	{0x4C4, 0xA7}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */

	{0x4F8, 0x40}, /* QSERDES_RX_SIGDET_ENABLES */

	{0x500, 0x73}, /* QSERDES_RX_SIGDET_CNTRL */

	{0x504, 0x06}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */

	{0x64C, 0x48}, /* PCIE_USB3_PHY_RX_IDLE_DTCT_CNTRL */

	{0xB4, 0x01}, /* QSERDES_COM_SSC_EN_CENTER */

	{0xB8, 0x02}, /* QSERDES_COM_SSC_ADJ_PER1 */

	{0xC0, 0x31}, /* QSERDES_COM_SSC_PER1 */

	{0xC4, 0x01}, /* QSERDES_COM_SSC_PER2 */

	{0xC8, 0x19}, /* QSERDES_COM_SSC_STEP_SIZE1 */

	{0xCC, 0x19}, /* QSERDES_COM_SSC_STEP_SIZE2 */

	{0x64C, 0x48}, /* PCIE_USB3_PHY_RX_IDLE_DTCT_CNTRL */

	{0x654, 0x08}, /* PCIE_USB3_PHY_POWER_STATE_CONFIG2 */

	{0x65C, 0xE5}, /* PCIE_USB3_PHY_RCVR_DTCT_DLY_P1U2_L */

	{0x660, 0x03}, /* PCIE_USB3_PHY_RCVR_DTCT_DLY_P1U2_H */

	{0x6A0, 0x13}, /* PCIE_USB3_PHY_RXEQTRAINING_RUN_TIME */

	{0x66C, 0xFF}, /* PCIE_USB3_PHY_LOCK_DETECT_CONFIG1 */

	{0x674, 0x17}, /* PCIE_USB3_PHY_LOCK_DETECT_CONFIG3 */



	{-1, -1} /* terminating entry */

};